Author: cem
Date: Sat Feb 1 17:30:45 2020
New Revision: 357372
URL: https://svnweb.freebsd.org/changeset/base/357372
Log:
intel_hwpstate(4): Don't leak bound thread in error conditions
I don't know why a Skylake CPU with the HWP feature bit present would trap
on MSR reads of the HWP registers, but if this occurs, do not leave the
attach thread bound. This could conceivably cause reported hangs, although
I have no evidence that this is the cause.
Reported by: ae@, Andreas Nilsson <andrnils AT gmail.com>
X-MFC-With: r357002
Modified:
head/sys/x86/cpufreq/hwpstate_intel.c
Modified: head/sys/x86/cpufreq/hwpstate_intel.c
==============================================================================
--- head/sys/x86/cpufreq/hwpstate_intel.c Sat Feb 1 17:13:52 2020
(r357371)
+++ head/sys/x86/cpufreq/hwpstate_intel.c Sat Feb 1 17:30:45 2020
(r357372)
@@ -343,12 +343,20 @@ set_autonomous_hwp(struct hwp_softc *sc)
}
ret = rdmsr_safe(MSR_IA32_HWP_REQUEST, &sc->req);
- if (ret)
- return (ret);
+ if (ret) {
+ device_printf(dev,
+ "Failed to read HWP request MSR for cpu%d (%d)\n",
+ pc->pc_cpuid, ret);
+ goto out;
+ }
ret = rdmsr_safe(MSR_IA32_HWP_CAPABILITIES, &caps);
- if (ret)
- return (ret);
+ if (ret) {
+ device_printf(dev,
+ "Failed to read HWP capabilities MSR for cpu%d (%d)\n",
+ pc->pc_cpuid, ret);
+ goto out;
+ }
sc->high = IA32_HWP_CAPABILITIES_HIGHEST_PERFORMANCE(caps);
sc->guaranteed = IA32_HWP_CAPABILITIES_GUARANTEED_PERFORMANCE(caps);
@@ -372,7 +380,7 @@ set_autonomous_hwp(struct hwp_softc *sc)
ret = wrmsr_safe(MSR_IA32_HWP_REQUEST, sc->req);
if (ret) {
device_printf(dev,
- "Failed to setup autonomous HWP for cpu%d (file a bug)\n",
+ "Failed to setup autonomous HWP for cpu%d\n",
pc->pc_cpuid);
}
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