Author: kp
Date: Wed Jul  1 19:15:43 2020
New Revision: 362853
URL: https://svnweb.freebsd.org/changeset/base/362853

Log:
  riscv pmap: zero reserved pte bits in ppn
  
  The top 10 bits of a pte are reserved by specification[1] and are not part of
  the PPN.
  
  [1] 'Volume II: RISC-V Privileged Architectures V20190608-Priv-MSU-Ratified',
  '4.4.1 Addressing and Memory Protection', page 72: "The PTE format for Sv39 is
  shown in Figure 4.18. ... Bits 63–54 are reserved for future use and must be
  zeroed by software for forward compatibility."
  
  Submitted by: Nathaniel Filardo <nw...@cl.cam.ac.uk>
  Reviewed by:  kp, mhorne
  Differential Revision:        https://reviews.freebsd.org/D25523

Modified:
  head/sys/riscv/include/pte.h
  head/sys/riscv/riscv/pmap.c

Modified: head/sys/riscv/include/pte.h
==============================================================================
--- head/sys/riscv/include/pte.h        Wed Jul  1 19:12:47 2020        
(r362852)
+++ head/sys/riscv/include/pte.h        Wed Jul  1 19:15:43 2020        
(r362853)
@@ -83,6 +83,9 @@ typedef       uint64_t        pn_t;                   /* page 
number */
 #define        PTE_PROMOTE     (PTE_V | PTE_RWX | PTE_D | PTE_A | PTE_G | 
PTE_U | \
                         PTE_SW_MANAGED | PTE_SW_WIRED)
 
+/* Bits 63 - 54 are reserved for future use. */
+#define PTE_HI_MASK    0xFFC0000000000000ULL
+
 #define        PTE_PPN0_S      10
 #define        PTE_PPN1_S      19
 #define        PTE_PPN2_S      28

Modified: head/sys/riscv/riscv/pmap.c
==============================================================================
--- head/sys/riscv/riscv/pmap.c Wed Jul  1 19:12:47 2020        (r362852)
+++ head/sys/riscv/riscv/pmap.c Wed Jul  1 19:15:43 2020        (r362853)
@@ -339,7 +339,8 @@ pagezero(void *p)
 #define        pmap_l2_index(va)       (((va) >> L2_SHIFT) & Ln_ADDR_MASK)
 #define        pmap_l3_index(va)       (((va) >> L3_SHIFT) & Ln_ADDR_MASK)
 
-#define        PTE_TO_PHYS(pte)        ((pte >> PTE_PPN0_S) * PAGE_SIZE)
+#define        PTE_TO_PHYS(pte) \
+    ((((pte) & ~PTE_HI_MASK) >> PTE_PPN0_S) * PAGE_SIZE)
 
 static __inline pd_entry_t *
 pmap_l1(pmap_t pmap, vm_offset_t va)
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