Author: mav
Date: Mon Jul 13 16:23:02 2020
New Revision: 363157
URL: https://svnweb.freebsd.org/changeset/base/363157
Log:
Update AMD Zen1 and add Zen2 events mapping.
MFC after: 2 weeks
Added:
- copied from r363156, head/lib/libpmc/pmu-events/arch/x86/amdfam17h/
head/lib/libpmc/pmu-events/arch/x86/amdzen1/branch.json (contents, props
changed)
head/lib/libpmc/pmu-events/arch/x86/amdzen2/branch.json (contents, props
changed)
head/lib/libpmc/pmu-events/arch/x86/amdzen2/cache.json (contents, props
changed)
head/lib/libpmc/pmu-events/arch/x86/amdzen2/core.json (contents, props
changed)
head/lib/libpmc/pmu-events/arch/x86/amdzen2/floating-point.json (contents,
props changed)
head/lib/libpmc/pmu-events/arch/x86/amdzen2/memory.json (contents, props
changed)
head/lib/libpmc/pmu-events/arch/x86/amdzen2/other.json (contents, props
changed)
Directory Properties:
head/lib/libpmc/pmu-events/arch/x86/amdzen1/ (props changed)
head/lib/libpmc/pmu-events/arch/x86/amdzen2/ (props changed)
Deleted:
head/lib/libpmc/pmu-events/arch/x86/amdfam17h/
Modified:
head/lib/libpmc/pmu-events/arch/x86/amdzen1/cache.json (contents, props
changed)
head/lib/libpmc/pmu-events/arch/x86/amdzen1/core.json (contents, props
changed)
head/lib/libpmc/pmu-events/arch/x86/amdzen1/floating-point.json (contents,
props changed)
head/lib/libpmc/pmu-events/arch/x86/amdzen1/memory.json (contents, props
changed)
head/lib/libpmc/pmu-events/arch/x86/amdzen1/other.json (contents, props
changed)
head/lib/libpmc/pmu-events/arch/x86/mapfile.csv
Added: head/lib/libpmc/pmu-events/arch/x86/amdzen1/branch.json
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ head/lib/libpmc/pmu-events/arch/x86/amdzen1/branch.json Mon Jul 13
16:23:02 2020 (r363157)
@@ -0,0 +1,23 @@
+[
+ {
+ "EventName": "bp_l1_btb_correct",
+ "EventCode": "0x8a",
+ "BriefDescription": "L1 BTB Correction."
+ },
+ {
+ "EventName": "bp_l2_btb_correct",
+ "EventCode": "0x8b",
+ "BriefDescription": "L2 BTB Correction."
+ },
+ {
+ "EventName": "bp_dyn_ind_pred",
+ "EventCode": "0x8e",
+ "BriefDescription": "Dynamic Indirect Predictions.",
+ "PublicDescription": "Indirect Branch Prediction for potential
multi-target branch (speculative)."
+ },
+ {
+ "EventName": "bp_de_redirect",
+ "EventCode": "0x91",
+ "BriefDescription": "Decoder Overrides Existing Branch Prediction
(speculative)."
+ }
+]
Modified: head/lib/libpmc/pmu-events/arch/x86/amdzen1/cache.json
==============================================================================
--- head/lib/libpmc/pmu-events/arch/x86/amdfam17h/cache.json Mon Jul 13
15:52:57 2020 (r363156)
+++ head/lib/libpmc/pmu-events/arch/x86/amdzen1/cache.json Mon Jul 13
16:23:02 2020 (r363157)
@@ -1,332 +1,294 @@
[
- {
- "EventName": "ic_fw32",
- "EventCode": "0x80",
- "BriefDescription": "The number of 32B fetch windows transferred from IC pipe
to DE instruction decoder (includes non-cacheable and cacheable fill
responses)."
- },
- {
- "EventName": "ic_fw32_miss",
- "EventCode": "0x81",
- "BriefDescription": "The number of 32B fetch windows tried to read the L1 IC
and missed in the full tag."
- },
- {
- "EventName": "ic_cache_fill_l2",
- "EventCode": "0x82",
- "BriefDescription": "The number of 64 byte instruction cache line was
fulfilled from the L2 cache."
- },
- {
- "EventName": "ic_cache_fill_sys",
- "EventCode": "0x83",
- "BriefDescription": "The number of 64 byte instruction cache line fulfilled
from system memory or another cache."
- },
- {
- "EventName": "bp_l1_tlb_miss_l2_hit",
- "EventCode": "0x84",
- "BriefDescription": "The number of instruction fetches that miss in the L1
ITLB but hit in the L2 ITLB."
- },
- {
- "EventName": "bp_l1_tlb_miss_l2_miss",
- "EventCode": "0x85",
- "BriefDescription": "The number of instruction fetches that miss in both the
L1 and L2 TLBs."
- },
- {
- "EventName": "bp_snp_re_sync",
- "EventCode": "0x86",
- "BriefDescription": "The number of pipeline restarts caused by invalidating
probes that hit on the instruction stream currently being executed. This would
happen if the active instruction stream was being modified by another processor
in an MP system - typically a highly unlikely event."
- },
- {
- "EventName": "ic_fetch_stall.ic_stall_any",
- "EventCode": "0x87",
- "BriefDescription": "IC pipe was stalled during this clock cycle for any
reason (nothing valid in pipe ICM1).",
- "PublicDescription": "Instruction Pipe Stall. IC pipe was stalled during this
clock cycle for any reason (nothing valid in pipe ICM1).",
- "UMask": "0x4"
- },
- {
- "EventName": "ic_fetch_stall.ic_stall_dq_empty",
- "EventCode": "0x87",
- "BriefDescription": "IC pipe was stalled during this clock cycle (including
IC to OC fetches) due to DQ empty.",
- "PublicDescription": "Instruction Pipe Stall. IC pipe was stalled during this
clock cycle (including IC to OC fetches) due to DQ empty.",
- "UMask": "0x2"
- },
- {
- "EventName": "ic_fetch_stall.ic_stall_back_pressure",
- "EventCode": "0x87",
- "BriefDescription": "IC pipe was stalled during this clock cycle (including
IC to OC fetches) due to back-pressure.",
- "PublicDescription": "Instruction Pipe Stall. IC pipe was stalled during this
clock cycle (including IC to OC fetches) due to back-pressure.",
- "UMask": "0x1"
- },
- {
- "EventName": "bp_l1_btb_correct",
- "EventCode": "0x8a",
- "BriefDescription": "L1 BTB Correction."
- },
- {
- "EventName": "bp_l2_btb_correct",
- "EventCode": "0x8b",
- "BriefDescription": "L2 BTB Correction."
- },
- {
- "EventName": "ic_cache_inval.l2_invalidating_probe",
- "EventCode": "0x8c",
- "BriefDescription": "IC line invalidated due to L2 invalidating probe
(external or LS).",
- "PublicDescription": "The number of instruction cache lines invalidated. A
non-SMC event is CMC (cross modifying code), either from the other thread of
the core or another core. IC line invalidated due to L2 invalidating probe
(external or LS).",
- "UMask": "0x2"
- },
- {
- "EventName": "ic_cache_inval.fill_invalidated",
- "EventCode": "0x8c",
- "BriefDescription": "IC line invalidated due to overwriting fill response.",
- "PublicDescription": "The number of instruction cache lines invalidated. A
non-SMC event is CMC (cross modifying code), either from the other thread of
the core or another core. IC line invalidated due to overwriting fill
response.",
- "UMask": "0x1"
- },
- {
- "EventName": "bp_tlb_rel",
- "EventCode": "0x99",
- "BriefDescription": "The number of ITLB reload requests."
- },
- {
- "EventName": "ic_oc_mode_switch.oc_ic_mode_switch",
- "EventCode": "0x28a",
- "BriefDescription": "OC to IC mode switch.",
- "PublicDescription": "OC Mode Switch. OC to IC mode switch.",
- "UMask": "0x2"
- },
- {
- "EventName": "ic_oc_mode_switch.ic_oc_mode_switch",
- "EventCode": "0x28a",
- "BriefDescription": "IC to OC mode switch.",
- "PublicDescription": "OC Mode Switch. IC to OC mode switch.",
- "UMask": "0x1"
- },
- {
- "EventName": "l2_request_g1.rd_blk_l",
- "EventCode": "0x60",
- "BriefDescription": "Requests to L2 Group1.",
- "PublicDescription": "Requests to L2 Group1.",
- "UMask": "0x80"
- },
- {
- "EventName": "l2_request_g1.rd_blk_x",
- "EventCode": "0x60",
- "BriefDescription": "Requests to L2 Group1.",
- "PublicDescription": "Requests to L2 Group1.",
- "UMask": "0x40"
- },
- {
- "EventName": "l2_request_g1.ls_rd_blk_c_s",
- "EventCode": "0x60",
- "BriefDescription": "Requests to L2 Group1.",
- "PublicDescription": "Requests to L2 Group1.",
- "UMask": "0x20"
- },
- {
- "EventName": "l2_request_g1.cacheable_ic_read",
- "EventCode": "0x60",
- "BriefDescription": "Requests to L2 Group1.",
- "PublicDescription": "Requests to L2 Group1.",
- "UMask": "0x10"
- },
- {
- "EventName": "l2_request_g1.change_to_x",
- "EventCode": "0x60",
- "BriefDescription": "Requests to L2 Group1.",
- "PublicDescription": "Requests to L2 Group1.",
- "UMask": "0x8"
- },
- {
- "EventName": "l2_request_g1.prefetch_l2",
- "EventCode": "0x60",
- "BriefDescription": "Requests to L2 Group1.",
- "PublicDescription": "Requests to L2 Group1.",
- "UMask": "0x4"
- },
- {
- "EventName": "l2_request_g1.l2_hw_pf",
- "EventCode": "0x60",
- "BriefDescription": "Requests to L2 Group1.",
- "PublicDescription": "Requests to L2 Group1.",
- "UMask": "0x2"
- },
- {
- "EventName": "l2_request_g1.other_requests",
- "EventCode": "0x60",
- "BriefDescription": "Events covered by l2_request_g2.",
- "PublicDescription": "Requests to L2 Group1. Events covered by
l2_request_g2.",
- "UMask": "0x1"
- },
- {
- "EventName": "l2_request_g2.group1",
- "EventCode": "0x61",
- "BriefDescription": "All Group 1 commands not in unit0.",
- "PublicDescription": "Multi-events in that LS and IF requests can be received
simultaneous. All Group 1 commands not in unit0.",
- "UMask": "0x80"
- },
- {
- "EventName": "l2_request_g2.ls_rd_sized",
- "EventCode": "0x61",
- "BriefDescription": "RdSized, RdSized32, RdSized64.",
- "PublicDescription": "Multi-events in that LS and IF requests can be received
simultaneous. RdSized, RdSized32, RdSized64.",
- "UMask": "0x40"
- },
- {
- "EventName": "l2_request_g2.ls_rd_sized_nc",
- "EventCode": "0x61",
- "BriefDescription": "RdSizedNC, RdSized32NC, RdSized64NC.",
- "PublicDescription": "Multi-events in that LS and IF requests can be received
simultaneous. RdSizedNC, RdSized32NC, RdSized64NC.",
- "UMask": "0x20"
- },
- {
- "EventName": "l2_request_g2.ic_rd_sized",
- "EventCode": "0x61",
- "BriefDescription": "Multi-events in that LS and IF requests can be received
simultaneous.",
- "PublicDescription": "Multi-events in that LS and IF requests can be received
simultaneous.",
- "UMask": "0x10"
- },
- {
- "EventName": "l2_request_g2.ic_rd_sized_nc",
- "EventCode": "0x61",
- "BriefDescription": "Multi-events in that LS and IF requests can be received
simultaneous.",
- "PublicDescription": "Multi-events in that LS and IF requests can be received
simultaneous.",
- "UMask": "0x8"
- },
- {
- "EventName": "l2_request_g2.smc_inval",
- "EventCode": "0x61",
- "BriefDescription": "Multi-events in that LS and IF requests can be received
simultaneous.",
- "PublicDescription": "Multi-events in that LS and IF requests can be received
simultaneous.",
- "UMask": "0x4"
- },
- {
- "EventName": "l2_request_g2.bus_locks_originator",
- "EventCode": "0x61",
- "BriefDescription": "Multi-events in that LS and IF requests can be received
simultaneous.",
- "PublicDescription": "Multi-events in that LS and IF requests can be received
simultaneous.",
- "UMask": "0x2"
- },
- {
- "EventName": "l2_request_g2.bus_locks_responses",
- "EventCode": "0x61",
- "BriefDescription": "Multi-events in that LS and IF requests can be received
simultaneous.",
- "PublicDescription": "Multi-events in that LS and IF requests can be received
simultaneous.",
- "UMask": "0x1"
- },
- {
- "EventName": "l2_latency.l2_cycles_waiting_on_fills",
- "EventCode": "0x62",
- "BriefDescription": "Total cycles spent waiting for L2 fills to complete from
L3 or memory, divided by four. This may be used to calculate average latency by
multiplying this count by four and then dividing by the total number of L2
fills (unit mask l2_request_g1 == FEh). Event counts are for both threads. To
calculate average latency, the number of fills from both threads must be used.",
- "PublicDescription": "Total cycles spent waiting for L2 fills to complete
from L3 or memory, divided by four. This may be used to calculate average
latency by multiplying this count by four and then dividing by the total number
of L2 fills (unit mask l2_request_g1 == FEh). Event counts are for both
threads. To calculate average latency, the number of fills from both threads
must be used.",
- "UMask": "0x1"
- },
- {
- "EventName": "l2_wbc_req.wcb_write",
- "EventCode": "0x63",
- "BriefDescription": "LS to L2 WBC requests.",
- "PublicDescription": "LS to L2 WBC requests.",
- "UMask": "0x40"
- },
- {
- "EventName": "l2_wbc_req.wcb_close",
- "EventCode": "0x63",
- "BriefDescription": "LS to L2 WBC requests.",
- "PublicDescription": "LS to L2 WBC requests.",
- "UMask": "0x20"
- },
- {
- "EventName": "l2_wbc_req.cache_line_flush",
- "EventCode": "0x63",
- "BriefDescription": "LS to L2 WBC requests.",
- "PublicDescription": "LS to L2 WBC requests.",
- "UMask": "0x10"
- },
- {
- "EventName": "l2_wbc_req.i_line_flush",
- "EventCode": "0x63",
- "BriefDescription": "LS to L2 WBC requests.",
- "PublicDescription": "LS to L2 WBC requests.",
- "UMask": "0x8"
- },
- {
- "EventName": "l2_wbc_req.zero_byte_store",
- "EventCode": "0x63",
- "BriefDescription": "This becomes WriteNoData at SDP; this count does not
include DVM Sync Ops and bus locks which are counted in l2_request_g2.",
- "PublicDescription": "LS to L2 WBC requests. This becomes WriteNoData at SDP;
this count does not include DVM Sync Ops and bus locks which are counted in
l2_request_g2.",
- "UMask": "0x4"
- },
- {
- "EventName": "l2_wbc_req.local_ic_clr",
- "EventCode": "0x63",
- "BriefDescription": "Local IC Clear.",
- "PublicDescription": "LS to L2 WBC requests. Local IC Clear.",
- "UMask": "0x2"
- },
- {
- "EventName": "l2_wbc_req.cl_zero",
- "EventCode": "0x63",
- "BriefDescription": "Cache Line Zero.",
- "PublicDescription": "LS to L2 WBC requests. Cache Line Zero.",
- "UMask": "0x1"
- },
- {
- "EventName": "l2_cache_req_stat.ls_rd_blk_cs",
- "EventCode": "0x64",
- "BriefDescription": "LS ReadBlock C/S Hit.",
- "PublicDescription": "This event does not count accesses to the L2 cache by
the L2 prefetcher, but it does count accesses by the L1 prefetcher. LS
ReadBlock C/S Hit.",
- "UMask": "0x80"
- },
- {
- "EventName": "l2_cache_req_stat.ls_rd_blk_l_hit_x",
- "EventCode": "0x64",
- "BriefDescription": "LS Read Block L Hit X.",
- "PublicDescription": "This event does not count accesses to the L2 cache by
the L2 prefetcher, but it does count accesses by the L1 prefetcher. LS Read
Block L Hit X.",
- "UMask": "0x40"
- },
- {
- "EventName": "l2_cache_req_stat.ls_rd_blk_l_hit_s",
- "EventCode": "0x64",
- "BriefDescription": "LsRdBlkL Hit Shared.",
- "PublicDescription": "This event does not count accesses to the L2 cache by
the L2 prefetcher, but it does count accesses by the L1 prefetcher. LsRdBlkL
Hit Shared.",
- "UMask": "0x20"
- },
- {
- "EventName": "l2_cache_req_stat.ls_rd_blk_x",
- "EventCode": "0x64",
- "BriefDescription": "LsRdBlkX/ChgToX Hit X. Count RdBlkX finding Shared as a
Miss.",
- "PublicDescription": "This event does not count accesses to the L2 cache by
the L2 prefetcher, but it does count accesses by the L1 prefetcher.
LsRdBlkX/ChgToX Hit X. Count RdBlkX finding Shared as a Miss.",
- "UMask": "0x10"
- },
- {
- "EventName": "l2_cache_req_stat.ls_rd_blk_c",
- "EventCode": "0x64",
- "BriefDescription": "LS Read Block C S L X Change to X Miss.",
- "PublicDescription": "This event does not count accesses to the L2 cache by
the L2 prefetcher, but it does count accesses by the L1 prefetcher. LS Read
Block C S L X Change to X Miss.",
- "UMask": "0x8"
- },
- {
- "EventName": "l2_cache_req_stat.ic_fill_hit_x",
- "EventCode": "0x64",
- "BriefDescription": "IC Fill Hit Exclusive Stale.",
- "PublicDescription": "This event does not count accesses to the L2 cache by
the L2 prefetcher, but it does count accesses by the L1 prefetcher. IC Fill Hit
Exclusive Stale.",
- "UMask": "0x4"
- },
- {
- "EventName": "l2_cache_req_stat.ic_fill_hit_s",
- "EventCode": "0x64",
- "BriefDescription": "IC Fill Hit Shared.",
- "PublicDescription": "This event does not count accesses to the L2 cache by
the L2 prefetcher, but it does count accesses by the L1 prefetcher. IC Fill Hit
Shared.",
- "UMask": "0x2"
- },
- {
- "EventName": "l2_cache_req_stat.ic_fill_miss",
- "EventCode": "0x64",
- "BriefDescription": "IC Fill Miss.",
- "PublicDescription": "This event does not count accesses to the L2 cache by
the L2 prefetcher, but it does count accesses by the L1 prefetcher. IC Fill
Miss.",
- "UMask": "0x1"
- },
- {
- "EventName": "l2_fill_pending.l2_fill_busy",
- "EventCode": "0x6d",
- "BriefDescription": "Total cycles spent with one or more fill requests in
flight from L2.",
- "PublicDescription": "Total cycles spent with one or more fill requests in
flight from L2.",
- "UMask": "0x1"
- }
+ {
+ "EventName": "ic_fw32",
+ "EventCode": "0x80",
+ "BriefDescription": "The number of 32B fetch windows transferred from IC
pipe to DE instruction decoder (includes non-cacheable and cacheable fill
responses)."
+ },
+ {
+ "EventName": "ic_fw32_miss",
+ "EventCode": "0x81",
+ "BriefDescription": "The number of 32B fetch windows tried to read the L1
IC and missed in the full tag."
+ },
+ {
+ "EventName": "ic_cache_fill_l2",
+ "EventCode": "0x82",
+ "BriefDescription": "The number of 64 byte instruction cache line was
fulfilled from the L2 cache."
+ },
+ {
+ "EventName": "ic_cache_fill_sys",
+ "EventCode": "0x83",
+ "BriefDescription": "The number of 64 byte instruction cache line
fulfilled from system memory or another cache."
+ },
+ {
+ "EventName": "bp_l1_tlb_miss_l2_hit",
+ "EventCode": "0x84",
+ "BriefDescription": "The number of instruction fetches that miss in the L1
ITLB but hit in the L2 ITLB."
+ },
+ {
+ "EventName": "bp_l1_tlb_miss_l2_miss",
+ "EventCode": "0x85",
+ "BriefDescription": "The number of instruction fetches that miss in both
the L1 and L2 TLBs."
+ },
+ {
+ "EventName": "bp_snp_re_sync",
+ "EventCode": "0x86",
+ "BriefDescription": "The number of pipeline restarts caused by
invalidating probes that hit on the instruction stream currently being
executed. This would happen if the active instruction stream was being modified
by another processor in an MP system - typically a highly unlikely event."
+ },
+ {
+ "EventName": "ic_fetch_stall.ic_stall_any",
+ "EventCode": "0x87",
+ "BriefDescription": "Instruction Pipe Stall. IC pipe was stalled during
this clock cycle for any reason (nothing valid in pipe ICM1).",
+ "UMask": "0x4"
+ },
+ {
+ "EventName": "ic_fetch_stall.ic_stall_dq_empty",
+ "EventCode": "0x87",
+ "BriefDescription": "Instruction Pipe Stall. IC pipe was stalled during
this clock cycle (including IC to OC fetches) due to DQ empty.",
+ "UMask": "0x2"
+ },
+ {
+ "EventName": "ic_fetch_stall.ic_stall_back_pressure",
+ "EventCode": "0x87",
+ "BriefDescription": "Instruction Pipe Stall. IC pipe was stalled during
this clock cycle (including IC to OC fetches) due to back-pressure.",
+ "UMask": "0x1"
+ },
+ {
+ "EventName": "ic_cache_inval.l2_invalidating_probe",
+ "EventCode": "0x8c",
+ "BriefDescription": "IC line invalidated due to L2 invalidating probe
(external or LS). The number of instruction cache lines invalidated. A non-SMC
event is CMC (cross modifying code), either from the other thread of the core
or another core.",
+ "UMask": "0x2"
+ },
+ {
+ "EventName": "ic_cache_inval.fill_invalidated",
+ "EventCode": "0x8c",
+ "BriefDescription": "IC line invalidated due to overwriting fill response.
The number of instruction cache lines invalidated. A non-SMC event is CMC
(cross modifying code), either from the other thread of the core or another
core.",
+ "UMask": "0x1"
+ },
+ {
+ "EventName": "bp_tlb_rel",
+ "EventCode": "0x99",
+ "BriefDescription": "The number of ITLB reload requests."
+ },
+ {
+ "EventName": "l2_request_g1.rd_blk_l",
+ "EventCode": "0x60",
+ "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data
cache reads (including hardware and software prefetch).",
+ "UMask": "0x80"
+ },
+ {
+ "EventName": "l2_request_g1.rd_blk_x",
+ "EventCode": "0x60",
+ "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data
cache stores.",
+ "UMask": "0x40"
+ },
+ {
+ "EventName": "l2_request_g1.ls_rd_blk_c_s",
+ "EventCode": "0x60",
+ "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data
cache shared reads.",
+ "UMask": "0x20"
+ },
+ {
+ "EventName": "l2_request_g1.cacheable_ic_read",
+ "EventCode": "0x60",
+ "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common).
Instruction cache reads.",
+ "UMask": "0x10"
+ },
+ {
+ "EventName": "l2_request_g1.change_to_x",
+ "EventCode": "0x60",
+ "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data
cache state change requests. Request change to writable, check L2 for current
state.",
+ "UMask": "0x8"
+ },
+ {
+ "EventName": "l2_request_g1.prefetch_l2_cmd",
+ "EventCode": "0x60",
+ "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common).
PrefetchL2Cmd.",
+ "UMask": "0x4"
+ },
+ {
+ "EventName": "l2_request_g1.l2_hw_pf",
+ "EventCode": "0x60",
+ "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). L2
Prefetcher. All prefetches accepted by L2 pipeline, hit or miss. Types of PF
and L2 hit/miss broken out in a separate perfmon event.",
+ "UMask": "0x2"
+ },
+ {
+ "EventName": "l2_request_g1.group2",
+ "EventCode": "0x60",
+ "BriefDescription": "Miscellaneous events covered in more detail by
l2_request_g2 (PMCx061).",
+ "UMask": "0x1"
+ },
+ {
+ "EventName": "l2_request_g2.group1",
+ "EventCode": "0x61",
+ "BriefDescription": "Miscellaneous events covered in more detail by
l2_request_g1 (PMCx060).",
+ "UMask": "0x80"
+ },
+ {
+ "EventName": "l2_request_g2.ls_rd_sized",
+ "EventCode": "0x61",
+ "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data
cache read sized.",
+ "UMask": "0x40"
+ },
+ {
+ "EventName": "l2_request_g2.ls_rd_sized_nc",
+ "EventCode": "0x61",
+ "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data
cache read sized non-cacheable.",
+ "UMask": "0x20"
+ },
+ {
+ "EventName": "l2_request_g2.ic_rd_sized",
+ "EventCode": "0x61",
+ "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare).
Instruction cache read sized.",
+ "UMask": "0x10"
+ },
+ {
+ "EventName": "l2_request_g2.ic_rd_sized_nc",
+ "EventCode": "0x61",
+ "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare).
Instruction cache read sized non-cacheable.",
+ "UMask": "0x8"
+ },
+ {
+ "EventName": "l2_request_g2.smc_inval",
+ "EventCode": "0x61",
+ "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare).
Self-modifying code invalidates.",
+ "UMask": "0x4"
+ },
+ {
+ "EventName": "l2_request_g2.bus_locks_originator",
+ "EventCode": "0x61",
+ "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Bus
locks.",
+ "UMask": "0x2"
+ },
+ {
+ "EventName": "l2_request_g2.bus_locks_responses",
+ "EventCode": "0x61",
+ "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Bus lock
response.",
+ "UMask": "0x1"
+ },
+ {
+ "EventName": "l2_latency.l2_cycles_waiting_on_fills",
+ "EventCode": "0x62",
+ "BriefDescription": "Total cycles spent waiting for L2 fills to complete
from L3 or memory, divided by four. Event counts are for both threads. To
calculate average latency, the number of fills from both threads must be used.",
+ "UMask": "0x1"
+ },
+ {
+ "EventName": "l2_wcb_req.wcb_write",
+ "EventCode": "0x63",
+ "BriefDescription": "LS to L2 WCB write requests. LS (Load/Store unit) to
L2 WCB (Write Combining Buffer) write requests.",
+ "UMask": "0x40"
+ },
+ {
+ "EventName": "l2_wcb_req.wcb_close",
+ "EventCode": "0x63",
+ "BriefDescription": "LS to L2 WCB close requests. LS (Load/Store unit) to
L2 WCB (Write Combining Buffer) close requests.",
+ "UMask": "0x20"
+ },
+ {
+ "EventName": "l2_wcb_req.zero_byte_store",
+ "EventCode": "0x63",
+ "BriefDescription": "LS to L2 WCB zero byte store requests. LS (Load/Store
unit) to L2 WCB (Write Combining Buffer) zero byte store requests.",
+ "UMask": "0x4"
+ },
+ {
+ "EventName": "l2_wcb_req.cl_zero",
+ "EventCode": "0x63",
+ "BriefDescription": "LS to L2 WCB cache line zeroing requests. LS
(Load/Store unit) to L2 WCB (Write Combining Buffer) cache line zeroing
requests.",
+ "UMask": "0x1"
+ },
+ {
+ "EventName": "l2_cache_req_stat.ls_rd_blk_cs",
+ "EventCode": "0x64",
+ "BriefDescription": "Core to L2 cacheable request access status (not
including L2 Prefetch). Data cache shared read hit in L2",
+ "UMask": "0x80"
+ },
+ {
+ "EventName": "l2_cache_req_stat.ls_rd_blk_l_hit_x",
+ "EventCode": "0x64",
+ "BriefDescription": "Core to L2 cacheable request access status (not
including L2 Prefetch). Data cache read hit in L2.",
+ "UMask": "0x40"
+ },
+ {
+ "EventName": "l2_cache_req_stat.ls_rd_blk_l_hit_s",
+ "EventCode": "0x64",
+ "BriefDescription": "Core to L2 cacheable request access status (not
including L2 Prefetch). Data cache read hit on shared line in L2.",
+ "UMask": "0x20"
+ },
+ {
+ "EventName": "l2_cache_req_stat.ls_rd_blk_x",
+ "EventCode": "0x64",
+ "BriefDescription": "Core to L2 cacheable request access status (not
including L2 Prefetch). Data cache store or state change hit in L2.",
+ "UMask": "0x10"
+ },
+ {
+ "EventName": "l2_cache_req_stat.ls_rd_blk_c",
+ "EventCode": "0x64",
+ "BriefDescription": "Core to L2 cacheable request access status (not
including L2 Prefetch). Data cache request miss in L2 (all types).",
+ "UMask": "0x8"
+ },
+ {
+ "EventName": "l2_cache_req_stat.ic_fill_hit_x",
+ "EventCode": "0x64",
+ "BriefDescription": "Core to L2 cacheable request access status (not
including L2 Prefetch). Instruction cache hit modifiable line in L2.",
+ "UMask": "0x4"
+ },
+ {
+ "EventName": "l2_cache_req_stat.ic_fill_hit_s",
+ "EventCode": "0x64",
+ "BriefDescription": "Core to L2 cacheable request access status (not
including L2 Prefetch). Instruction cache hit clean line in L2.",
+ "UMask": "0x2"
+ },
+ {
+ "EventName": "l2_cache_req_stat.ic_fill_miss",
+ "EventCode": "0x64",
+ "BriefDescription": "Core to L2 cacheable request access status (not
including L2 Prefetch). Instruction cache request miss in L2.",
+ "UMask": "0x1"
+ },
+ {
+ "EventName": "l2_fill_pending.l2_fill_busy",
+ "EventCode": "0x6d",
+ "BriefDescription": "Cycles with fill pending from L2. Total cycles spent
with one or more fill requests in flight from L2.",
+ "UMask": "0x1"
+ },
+ {
+ "EventName": "l3_request_g1.caching_l3_cache_accesses",
+ "EventCode": "0x01",
+ "BriefDescription": "Caching: L3 cache accesses",
+ "UMask": "0x80",
+ "Unit": "L3PMC"
+ },
+ {
+ "EventName": "l3_lookup_state.all_l3_req_typs",
+ "EventCode": "0x04",
+ "BriefDescription": "All L3 Request Types",
+ "UMask": "0xff",
+ "Unit": "L3PMC"
+ },
+ {
+ "EventName": "l3_comb_clstr_state.other_l3_miss_typs",
+ "EventCode": "0x06",
+ "BriefDescription": "Other L3 Miss Request Types",
+ "UMask": "0xfe",
+ "Unit": "L3PMC"
+ },
+ {
+ "EventName": "l3_comb_clstr_state.request_miss",
+ "EventCode": "0x06",
+ "BriefDescription": "L3 cache misses",
+ "UMask": "0x01",
+ "Unit": "L3PMC"
+ },
+ {
+ "EventName": "xi_sys_fill_latency",
+ "EventCode": "0x90",
+ "BriefDescription": "L3 Cache Miss Latency. Total cycles for all
transactions divided by 16. Ignores SliceMask and ThreadMask.",
+ "UMask": "0x00",
+ "Unit": "L3PMC"
+ },
+ {
+ "EventName": "xi_ccx_sdp_req1.all_l3_miss_req_typs",
+ "EventCode": "0x9a",
+ "BriefDescription": "All L3 Miss Request Types. Ignores SliceMask and
ThreadMask.",
+ "UMask": "0x3f",
+ "Unit": "L3PMC"
+ }
]
Modified: head/lib/libpmc/pmu-events/arch/x86/amdzen1/core.json
==============================================================================
--- head/lib/libpmc/pmu-events/arch/x86/amdfam17h/core.json Mon Jul 13
15:52:57 2020 (r363156)
+++ head/lib/libpmc/pmu-events/arch/x86/amdzen1/core.json Mon Jul 13
16:23:02 2020 (r363157)
@@ -1,127 +1,125 @@
[
- {
- "EventName": "ex_ret_instr",
- "EventCode": "0xc0",
- "SampleAfterValue": "2000003",
- "BriefDescription": "Retired Instructions."
- },
- {
- "EventName": "ex_ret_cops",
- "EventCode": "0xc1",
- "SampleAfterValue": "2000003",
- "BriefDescription": "The number of uOps retired. This includes all processor
activity (instructions, exceptions, interrupts, microcode assists, etc.). The
number of events logged per cycle can vary from 0 to 4."
- },
- {
- "EventName": "ex_ret_brn",
- "EventCode": "0xc2",
- "SampleAfterValue": "2000003",
- "BriefDescription": "The number of branch instructions retired. This includes
all types of architectural control flow changes, including exceptions and
interrupts."
- },
- {
- "EventName": "ex_ret_brn_misp",
- "EventCode": "0xc3",
- "BriefDescription": "The number of branch instructions retired, of any type,
that were not correctly predicted. This includes those for which prediction is
not attempted (far control transfers, exceptions and interrupts)."
- },
- {
- "EventName": "ex_ret_brn_tkn",
- "EventCode": "0xc4",
- "BriefDescription": "The number of taken branches that were retired. This
includes all types of architectural control flow changes, including exceptions
and interrupts."
- },
- {
- "EventName": "ex_ret_brn_tkn_misp",
- "EventCode": "0xc5",
- "BriefDescription": "The number of retired taken branch instructions that
were mispredicted."
- },
- {
- "EventName": "ex_ret_brn_far",
- "EventCode": "0xc6",
- "BriefDescription": "The number of far control transfers retired including
far call/jump/return, IRET, SYSCALL and SYSRET, plus exceptions and interrupts.
Far control transfers are not subject to branch prediction."
- },
- {
- "EventName": "ex_ret_brn_resync",
- "EventCode": "0xc7",
- "BriefDescription": "The number of resync branches. These reflect pipeline
restarts due to certain microcode assists and events such as writes to the
active instruction stream, among other things. Each occurrence reflects a
restart penalty similar to a branch mispredict. This is relatively rare."
- },
- {
- "EventName": "ex_ret_near_ret",
- "EventCode": "0xc8",
- "BriefDescription": "The number of near return instructions (RET or RET Iw)
retired."
- },
- {
- "EventName": "ex_ret_near_ret_mispred",
- "EventCode": "0xc9",
- "BriefDescription": "The number of near returns retired that were not
correctly predicted by the return address predictor. Each such mispredict
incurs the same penalty as a mispredicted conditional branch instruction."
- },
- {
- "EventName": "ex_ret_brn_ind_misp",
- "EventCode": "0xca",
- "BriefDescription": "Retired Indirect Branch Instructions Mispredicted."
- },
- {
- "EventName": "ex_ret_mmx_fp_instr.sse_instr",
- "EventCode": "0xcb",
- "BriefDescription": "SSE instructions (SSE, SSE2, SSE3, SSSE3, SSE4A, SSE41,
SSE42, AVX).",
- "PublicDescription": "The number of MMX, SSE or x87 instructions retired. The
UnitMask allows the selection of the individual classes of instructions as
given in the table. Each increment represents one complete instruction. Since
this event includes non-numeric instructions it is not suitable for measuring
MFLOPS. SSE instructions (SSE, SSE2, SSE3, SSSE3, SSE4A, SSE41, SSE42, AVX).",
- "UMask": "0x4"
- },
- {
- "EventName": "ex_ret_mmx_fp_instr.mmx_instr",
- "EventCode": "0xcb",
- "BriefDescription": "MMX instructions.",
- "PublicDescription": "The number of MMX, SSE or x87 instructions retired. The
UnitMask allows the selection of the individual classes of instructions as
given in the table. Each increment represents one complete instruction. Since
this event includes non-numeric instructions it is not suitable for measuring
MFLOPS. MMX instructions.",
- "UMask": "0x2"
- },
- {
- "EventName": "ex_ret_mmx_fp_instr.x87_instr",
- "EventCode": "0xcb",
- "BriefDescription": "x87 instructions.",
- "PublicDescription": "The number of MMX, SSE or x87 instructions retired. The
UnitMask allows the selection of the individual classes of instructions as
given in the table. Each increment represents one complete instruction. Since
this event includes non-numeric instructions it is not suitable for measuring
MFLOPS. x87 instructions.",
- "UMask": "0x1"
- },
- {
- "EventName": "ex_ret_cond",
- "EventCode": "0xd1",
- "BriefDescription": "Retired Conditional Branch Instructions."
- },
- {
- "EventName": "ex_ret_cond_misp",
- "EventCode": "0xd2",
- "BriefDescription": "Retired Conditional Branch Instructions Mispredicted."
- },
- {
- "EventName": "ex_div_busy",
- "EventCode": "0xd3",
- "BriefDescription": "Div Cycles Busy count."
- },
- {
- "EventName": "ex_div_count",
- "EventCode": "0xd4",
- "BriefDescription": "Div Op Count."
- },
- {
- "EventName": "ex_tagged_ibs_ops.ibs_count_rollover",
- "EventCode": "0x1cf",
- "BriefDescription": "Number of times an op could not be tagged by IBS because
of a previous tagged op that has not retired.",
- "PublicDescription": "Tagged IBS Ops. Number of times an op could not be
tagged by IBS because of a previous tagged op that has not retired.",
- "UMask": "0x4"
- },
- {
- "EventName": "ex_tagged_ibs_ops.ibs_tagged_ops_ret",
- "EventCode": "0x1cf",
- "BriefDescription": "Number of Ops tagged by IBS that retired.",
- "PublicDescription": "Tagged IBS Ops. Number of Ops tagged by IBS that
retired.",
- "UMask": "0x2"
- },
- {
- "EventName": "ex_tagged_ibs_ops.ibs_tagged_ops",
- "EventCode": "0x1cf",
- "BriefDescription": "Number of Ops tagged by IBS.",
- "PublicDescription": "Tagged IBS Ops. Number of Ops tagged by IBS.",
- "UMask": "0x1"
- },
- {
- "EventName": "ex_ret_fus_brnch_inst",
- "EventCode": "0x1d0",
- "BriefDescription": "The number of fused retired branch instructions retired
per cycle. The number of events logged per cycle can vary from 0 to 3."
- }
+ {
+ "EventName": "ex_ret_instr",
+ "EventCode": "0xc0",
+ "BriefDescription": "Retired Instructions."
+ },
+ {
+ "EventName": "ex_ret_cops",
+ "EventCode": "0xc1",
+ "BriefDescription": "Retired Uops.",
+ "PublicDescription": "The number of uOps retired. This includes all
processor activity (instructions, exceptions, interrupts, microcode assists,
etc.). The number of events logged per cycle can vary from 0 to 4."
+ },
+ {
+ "EventName": "ex_ret_brn",
+ "EventCode": "0xc2",
+ "BriefDescription": "Retired Branch Instructions.",
+ "PublicDescription": "The number of branch instructions retired. This
includes all types of architectural control flow changes, including exceptions
and interrupts."
+ },
+ {
+ "EventName": "ex_ret_brn_misp",
+ "EventCode": "0xc3",
+ "BriefDescription": "Retired Branch Instructions Mispredicted.",
+ "PublicDescription": "The number of branch instructions retired, of any
type, that were not correctly predicted. This includes those for which
prediction is not attempted (far control transfers, exceptions and interrupts)."
+ },
+ {
+ "EventName": "ex_ret_brn_tkn",
+ "EventCode": "0xc4",
+ "BriefDescription": "Retired Taken Branch Instructions.",
+ "PublicDescription": "The number of taken branches that were retired. This
includes all types of architectural control flow changes, including exceptions
and interrupts."
+ },
+ {
+ "EventName": "ex_ret_brn_tkn_misp",
+ "EventCode": "0xc5",
+ "BriefDescription": "Retired Taken Branch Instructions Mispredicted.",
+ "PublicDescription": "The number of retired taken branch instructions that
were mispredicted."
+ },
+ {
+ "EventName": "ex_ret_brn_far",
+ "EventCode": "0xc6",
+ "BriefDescription": "Retired Far Control Transfers.",
+ "PublicDescription": "The number of far control transfers retired
including far call/jump/return, IRET, SYSCALL and SYSRET, plus exceptions and
interrupts. Far control transfers are not subject to branch prediction."
+ },
+ {
+ "EventName": "ex_ret_brn_resync",
+ "EventCode": "0xc7",
+ "BriefDescription": "Retired Branch Resyncs.",
+ "PublicDescription": "The number of resync branches. These reflect
pipeline restarts due to certain microcode assists and events such as writes to
the active instruction stream, among other things. Each occurrence reflects a
restart penalty similar to a branch mispredict. This is relatively rare."
+ },
+ {
+ "EventName": "ex_ret_near_ret",
+ "EventCode": "0xc8",
+ "BriefDescription": "Retired Near Returns.",
+ "PublicDescription": "The number of near return instructions (RET or RET
Iw) retired."
+ },
+ {
+ "EventName": "ex_ret_near_ret_mispred",
+ "EventCode": "0xc9",
+ "BriefDescription": "Retired Near Returns Mispredicted.",
+ "PublicDescription": "The number of near returns retired that were not
correctly predicted by the return address predictor. Each such mispredict
incurs the same penalty as a mispredicted conditional branch instruction."
+ },
+ {
+ "EventName": "ex_ret_brn_ind_misp",
+ "EventCode": "0xca",
+ "BriefDescription": "Retired Indirect Branch Instructions Mispredicted.",
+ },
+ {
+ "EventName": "ex_ret_mmx_fp_instr.sse_instr",
+ "EventCode": "0xcb",
+ "BriefDescription": "SSE instructions (SSE, SSE2, SSE3, SSSE3, SSE4A,
SSE41, SSE42, AVX).",
+ "PublicDescription": "The number of MMX, SSE or x87 instructions retired.
The UnitMask allows the selection of the individual classes of instructions as
given in the table. Each increment represents one complete instruction. Since
this event includes non-numeric instructions it is not suitable for measuring
MFLOPS. SSE instructions (SSE, SSE2, SSE3, SSSE3, SSE4A, SSE41, SSE42, AVX).",
+ "UMask": "0x4"
+ },
+ {
+ "EventName": "ex_ret_mmx_fp_instr.mmx_instr",
+ "EventCode": "0xcb",
+ "BriefDescription": "MMX instructions.",
+ "PublicDescription": "The number of MMX, SSE or x87 instructions retired.
The UnitMask allows the selection of the individual classes of instructions as
given in the table. Each increment represents one complete instruction. Since
this event includes non-numeric instructions it is not suitable for measuring
MFLOPS. MMX instructions.",
+ "UMask": "0x2"
+ },
+ {
+ "EventName": "ex_ret_mmx_fp_instr.x87_instr",
+ "EventCode": "0xcb",
+ "BriefDescription": "x87 instructions.",
+ "PublicDescription": "The number of MMX, SSE or x87 instructions retired.
The UnitMask allows the selection of the individual classes of instructions as
given in the table. Each increment represents one complete instruction. Since
this event includes non-numeric instructions it is not suitable for measuring
MFLOPS. x87 instructions.",
+ "UMask": "0x1"
+ },
+ {
+ "EventName": "ex_ret_cond",
+ "EventCode": "0xd1",
+ "BriefDescription": "Retired Conditional Branch Instructions."
+ },
+ {
+ "EventName": "ex_div_busy",
+ "EventCode": "0xd3",
+ "BriefDescription": "Div Cycles Busy count."
+ },
+ {
+ "EventName": "ex_div_count",
+ "EventCode": "0xd4",
+ "BriefDescription": "Div Op Count."
+ },
+ {
+ "EventName": "ex_tagged_ibs_ops.ibs_count_rollover",
+ "EventCode": "0x1cf",
+ "BriefDescription": "Tagged IBS Ops. Number of times an op could not be
tagged by IBS because of a previous tagged op that has not retired.",
+ "UMask": "0x4"
+ },
+ {
+ "EventName": "ex_tagged_ibs_ops.ibs_tagged_ops_ret",
+ "EventCode": "0x1cf",
+ "BriefDescription": "Tagged IBS Ops. Number of Ops tagged by IBS that
retired.",
+ "UMask": "0x2"
+ },
+ {
+ "EventName": "ex_tagged_ibs_ops.ibs_tagged_ops",
+ "EventCode": "0x1cf",
+ "BriefDescription": "Tagged IBS Ops. Number of Ops tagged by IBS.",
+ "UMask": "0x1"
+ },
+ {
+ "EventName": "ex_ret_fus_brnch_inst",
+ "EventCode": "0x1d0",
+ "BriefDescription": "The number of fused retired branch instructions
retired per cycle. The number of events logged per cycle can vary from 0 to 3."
+ }
]
Modified: head/lib/libpmc/pmu-events/arch/x86/amdzen1/floating-point.json
==============================================================================
--- head/lib/libpmc/pmu-events/arch/x86/amdfam17h/floating-point.json Mon Jul
13 15:52:57 2020 (r363156)
+++ head/lib/libpmc/pmu-events/arch/x86/amdzen1/floating-point.json Mon Jul
13 16:23:02 2020 (r363157)
@@ -1,196 +1,224 @@
[
- {
- "EventName": "fpu_pipe_assignment.dual3",
- "EventCode": "0x00",
- "BriefDescription": "Total number multi-pipe uOps assigned to Pipe 3.",
- "PublicDescription": "The number of operations (uOps) and dual-pipe uOps
dispatched to each of the 4 FPU execution pipelines. This event reflects how
busy the FPU pipelines are and may be used for workload characterization. This
includes all operations performed by x87, MMXTM, and SSE instructions,
including moves. Each increment represents a one- cycle dispatch event. This
event is a speculative event. Since this event includes non-numeric operations
it is not suitable for measuring MFLOPS. Total number multi-pipe uOps assigned
to Pipe 3.",
- "UMask": "0x80"
- },
- {
- "EventName": "fpu_pipe_assignment.dual2",
- "EventCode": "0x00",
- "BriefDescription": "Total number multi-pipe uOps assigned to Pipe 2.",
- "PublicDescription": "The number of operations (uOps) and dual-pipe uOps
dispatched to each of the 4 FPU execution pipelines. This event reflects how
busy the FPU pipelines are and may be used for workload characterization. This
includes all operations performed by x87, MMXTM, and SSE instructions,
including moves. Each increment represents a one- cycle dispatch event. This
event is a speculative event. Since this event includes non-numeric operations
it is not suitable for measuring MFLOPS. Total number multi-pipe uOps assigned
to Pipe 2.",
- "UMask": "0x40"
- },
- {
- "EventName": "fpu_pipe_assignment.dual1",
- "EventCode": "0x00",
- "BriefDescription": "Total number multi-pipe uOps assigned to Pipe 1.",
- "PublicDescription": "The number of operations (uOps) and dual-pipe uOps
dispatched to each of the 4 FPU execution pipelines. This event reflects how
busy the FPU pipelines are and may be used for workload characterization. This
includes all operations performed by x87, MMXTM, and SSE instructions,
including moves. Each increment represents a one- cycle dispatch event. This
event is a speculative event. Since this event includes non-numeric operations
it is not suitable for measuring MFLOPS. Total number multi-pipe uOps assigned
to Pipe 1.",
- "UMask": "0x20"
- },
- {
- "EventName": "fpu_pipe_assignment.dual0",
- "EventCode": "0x00",
- "BriefDescription": "Total number multi-pipe uOps assigned to Pipe 0.",
- "PublicDescription": "The number of operations (uOps) and dual-pipe uOps
dispatched to each of the 4 FPU execution pipelines. This event reflects how
busy the FPU pipelines are and may be used for workload characterization. This
includes all operations performed by x87, MMXTM, and SSE instructions,
including moves. Each increment represents a one- cycle dispatch event. This
event is a speculative event. Since this event includes non-numeric operations
it is not suitable for measuring MFLOPS. Total number multi-pipe uOps assigned
to Pipe 0.",
- "UMask": "0x10"
- },
- {
- "EventName": "fpu_pipe_assignment.total3",
- "EventCode": "0x00",
- "BriefDescription": "Total number uOps assigned to Pipe 3.",
- "PublicDescription": "The number of operations (uOps) and dual-pipe uOps
dispatched to each of the 4 FPU execution pipelines. This event reflects how
busy the FPU pipelines are and may be used for workload characterization. This
includes all operations performed by x87, MMXTM, and SSE instructions,
including moves. Each increment represents a one- cycle dispatch event. This
event is a speculative event. Since this event includes non-numeric operations
it is not suitable for measuring MFLOPS. Total number uOps assigned to Pipe 3.",
- "UMask": "0x8"
- },
- {
- "EventName": "fpu_pipe_assignment.total2",
- "EventCode": "0x00",
- "BriefDescription": "Total number uOps assigned to Pipe 2.",
- "PublicDescription": "The number of operations (uOps) and dual-pipe uOps
dispatched to each of the 4 FPU execution pipelines. This event reflects how
busy the FPU pipelines are and may be used for workload characterization. This
includes all operations performed by x87, MMXTM, and SSE instructions,
including moves. Each increment represents a one- cycle dispatch event. This
event is a speculative event. Since this event includes non-numeric operations
it is not suitable for measuring MFLOPS. Total number uOps assigned to Pipe 2.",
- "UMask": "0x4"
- },
- {
- "EventName": "fpu_pipe_assignment.total1",
- "EventCode": "0x00",
- "BriefDescription": "Total number uOps assigned to Pipe 1.",
- "PublicDescription": "The number of operations (uOps) and dual-pipe uOps
dispatched to each of the 4 FPU execution pipelines. This event reflects how
busy the FPU pipelines are and may be used for workload characterization. This
includes all operations performed by x87, MMXTM, and SSE instructions,
including moves. Each increment represents a one- cycle dispatch event. This
event is a speculative event. Since this event includes non-numeric operations
it is not suitable for measuring MFLOPS. Total number uOps assigned to Pipe 1.",
- "UMask": "0x2"
- },
- {
- "EventName": "fpu_pipe_assignment.total0",
- "EventCode": "0x00",
- "BriefDescription": "Total number uOps assigned to Pipe 0.",
- "PublicDescription": "The number of operations (uOps) and dual-pipe uOps
dispatched to each of the 4 FPU execution pipelines. This event reflects how
busy the FPU pipelines are and may be used for workload characterization. This
includes all operations performed by x87, MMXTM, and SSE instructions,
including moves. Each increment represents a one- cycle dispatch event. This
event is a speculative event. Since this event includes non-numeric operations
it is not suitable for measuring MFLOPS. Total number uOps assigned to Pipe 0.",
- "UMask": "0x1"
- },
- {
- "EventName": "fp_sched_empty",
- "EventCode": "0x01",
- "BriefDescription": "This is a speculative event. The number of cycles in
which the FPU scheduler is empty. Note that some Ops like FP loads bypass the
scheduler."
- },
- {
- "EventName": "fp_retx87_fp_ops.div_sqr_r_ops",
- "EventCode": "0x02",
- "BriefDescription": "Divide and square root Ops.",
- "PublicDescription": "The number of x87 floating-point Ops that have retired.
The number of events logged per cycle can vary from 0 to 8. Divide and square
root Ops.",
- "UMask": "0x4"
- },
- {
- "EventName": "fp_retx87_fp_ops.mul_ops",
- "EventCode": "0x02",
- "BriefDescription": "Multiply Ops.",
- "PublicDescription": "The number of x87 floating-point Ops that have retired.
The number of events logged per cycle can vary from 0 to 8. Multiply Ops.",
- "UMask": "0x2"
- },
- {
- "EventName": "fp_retx87_fp_ops.add_sub_ops",
- "EventCode": "0x02",
- "BriefDescription": "Add/subtract Ops.",
- "PublicDescription": "The number of x87 floating-point Ops that have retired.
The number of events logged per cycle can vary from 0 to 8. Add/subtract Ops.",
- "UMask": "0x1"
- },
- {
- "EventName": "fp_ret_sse_avx_ops.dp_mult_add_flops",
- "EventCode": "0x03",
- "BriefDescription": "Double precision multiply-add FLOPS. Multiply-add counts
as 2 FLOPS.",
- "PublicDescription": "This is a retire-based event. The number of retired
SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64.
This event can count above 15. Double precision multiply-add FLOPS.
Multiply-add counts as 2 FLOPS.",
- "UMask": "0x80"
- },
- {
*** DIFF OUTPUT TRUNCATED AT 1000 LINES ***
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