Author: marius
Date: Sun May 2 16:46:20 2010
New Revision: 207522
URL: http://svn.freebsd.org/changeset/base/207522
Log:
MFC: r206450
Correct the DCR_IPE macro to refer to the right bit. Also improve the
associated comment as besides US-IV+ these bits are only available with
US-III++, i.e. the 1.2GHz version of the US-III+.
Modified:
stable/8/sys/sparc64/include/dcr.h
Directory Properties:
stable/8/sys/ (props changed)
stable/8/sys/amd64/include/xen/ (props changed)
stable/8/sys/cddl/contrib/opensolaris/ (props changed)
stable/8/sys/contrib/dev/acpica/ (props changed)
stable/8/sys/contrib/pf/ (props changed)
stable/8/sys/dev/xen/xenpci/ (props changed)
stable/8/sys/geom/sched/ (props changed)
Modified: stable/8/sys/sparc64/include/dcr.h
==============================================================================
--- stable/8/sys/sparc64/include/dcr.h Sun May 2 16:45:09 2010
(r207521)
+++ stable/8/sys/sparc64/include/dcr.h Sun May 2 16:46:20 2010
(r207522)
@@ -43,8 +43,8 @@
#define DCR_OBSDATA_CT_MASK
\
(((1UL << DCR_OBSDATA_CT_BITS) - 1) << DCR_OBSDATA_SHIFT)
-/* The following bits are valid for the UltraSPARC-III+/IV+ only. */
-#define DCR_IPE (1UL << 5)
+/* The following bits are valid for the UltraSPARC-III++/IV+ only. */
+#define DCR_IPE (1UL << 2)
#define DCR_OBSDATA_CTP_BITS 6
#define DCR_OBSDATA_CTP_MASK
\
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