Author: imp
Date: Thu Jul 15 01:58:20 2010
New Revision: 210100
URL: http://svn.freebsd.org/changeset/base/210100
Log:
Remove unused stuff from cpu.h.
Move inappropriate stuff in cpu.h elsewhere:
{s,g}et_intr_mask -> md_var.h
num_tlbentries -> tlb.h
Remove #define clockframe trapframe and fix clock, which was the only place
this was used.
All the rest of this stuff was unused.
# we're not quite minimal yet, since we duplicate a few status register things
# here...
Inspired by: bde@
Modified:
head/sys/mips/include/clock.h
head/sys/mips/include/cpu.h
head/sys/mips/include/md_var.h
head/sys/mips/include/tlb.h
Modified: head/sys/mips/include/clock.h
==============================================================================
--- head/sys/mips/include/clock.h Thu Jul 15 01:55:28 2010
(r210099)
+++ head/sys/mips/include/clock.h Thu Jul 15 01:58:20 2010
(r210100)
@@ -17,7 +17,7 @@
extern int cpu_clock;
-extern uint32_t clockintr(uint32_t, struct clockframe *);
+extern uint32_t clockintr(uint32_t, struct trapframe *);
#define wall_cmos_clock 0
#define adjkerntz 0
Modified: head/sys/mips/include/cpu.h
==============================================================================
--- head/sys/mips/include/cpu.h Thu Jul 15 01:55:28 2010 (r210099)
+++ head/sys/mips/include/cpu.h Thu Jul 15 01:58:20 2010 (r210100)
@@ -83,175 +83,34 @@
* Exported definitions unique to mips cpu support.
*/
-#define cpu_swapout(p) panic("cpu_swapout: can't get here");
-
#ifndef _LOCORE
#include <machine/cpufunc.h>
#include <machine/frame.h>
-/*
- * Arguments to hardclock and gatherstats encapsulate the previous
- * machine state in an opaque clockframe.
- */
-#define clockframe trapframe /* Use normal trap frame */
-
-#define CLKF_USERMODE(framep) ((framep)->sr & SR_KSU_USER)
-#define CLKF_PC(framep) ((framep)->pc)
-#define CLKF_INTR(framep) (0)
-#define MIPS_CLKF_INTR() (intr_nesting_level >= 1)
#define TRAPF_USERMODE(framep) (((framep)->sr & SR_KSU_USER) != 0)
#define TRAPF_PC(framep) ((framep)->pc)
#define cpu_getstack(td) ((td)->td_frame->sp)
+#define cpu_setstack(td, nsp) ((td)->td_frame->sp = (nsp))
+#define cpu_spinwait() /* nothing */
/*
* A machine-independent interface to the CPU's counter.
*/
-#define get_cyclecount() mips_rd_count()
-#endif /* !_LOCORE */
-
-/*
- * CTL_MACHDEP definitions.
- */
-#define CPU_CONSDEV 1 /* dev_t: console terminal
device */
-#define CPU_ADJKERNTZ 2 /* int: timezone offset
(seconds) */
-#define CPU_DISRTCSET 3 /* int: disable resettodr()
call */
-#define CPU_BOOTINFO 4 /* struct: bootinfo */
-#define CPU_WALLCLOCK 5 /* int: indicates wall CMOS
clock */
-#define CPU_MAXID 6 /* number of valid machdep ids
*/
-
-#define CTL_MACHDEP_NAMES { \
- { 0, 0 }, \
- { "console_device", CTLTYPE_STRUCT }, \
- { "adjkerntz", CTLTYPE_INT }, \
- { "disable_rtc_set", CTLTYPE_INT }, \
- { "bootinfo", CTLTYPE_STRUCT }, \
- { "wall_cmos_clock", CTLTYPE_INT }, \
+static __inline uint64_t
+get_cyclecount(void)
+{
+ return (mips_rd_count());
}
-
-/*
- * MIPS CPU types (cp_imp).
- */
-#define MIPS_R2000 0x01 /* MIPS R2000 CPU ISA I
*/
-#define MIPS_R3000 0x02 /* MIPS R3000 CPU ISA I
*/
-#define MIPS_R6000 0x03 /* MIPS R6000 CPU ISA II
*/
-#define MIPS_R4000 0x04 /* MIPS R4000/4400 CPU ISA III
*/
-#define MIPS_R3LSI 0x05 /* LSI Logic R3000 derivate ISA I
*/
-#define MIPS_R6000A 0x06 /* MIPS R6000A CPU ISA II
*/
-#define MIPS_R3IDT 0x07 /* IDT R3000 derivate ISA I
*/
-#define MIPS_R10000 0x09 /* MIPS R10000/T5 CPU ISA IV
*/
-#define MIPS_R4200 0x0a /* MIPS R4200 CPU (ICE) ISA III
*/
-#define MIPS_R4300 0x0b /* NEC VR4300 CPU ISA III
*/
-#define MIPS_R4100 0x0c /* NEC VR41xx CPU MIPS-16 ISA III
*/
-#define MIPS_R8000 0x10 /* MIPS R8000 Blackbird/TFP ISA IV
*/
-#define MIPS_R4600 0x20 /* QED R4600 Orion ISA III
*/
-#define MIPS_R4700 0x21 /* QED R4700 Orion ISA III
*/
-#define MIPS_R3TOSH 0x22 /* Toshiba R3000 based CPU ISA I
*/
-#define MIPS_R5000 0x23 /* MIPS R5000 CPU ISA IV
*/
-#define MIPS_RM7000 0x27 /* QED RM7000 CPU ISA IV
*/
-#define MIPS_RM52X0 0x28 /* QED RM52X0 CPU ISA IV
*/
-#define MIPS_VR5400 0x54 /* NEC Vr5400 CPU ISA IV+
*/
-#define MIPS_RM9000 0x34 /* E9000 CPU
*/
-
-/*
- * MIPS FPU types
- */
-#define MIPS_SOFT 0x00 /* Software emulation ISA I
*/
-#define MIPS_R2360 0x01 /* MIPS R2360 FPC ISA I
*/
-#define MIPS_R2010 0x02 /* MIPS R2010 FPC ISA I
*/
-#define MIPS_R3010 0x03 /* MIPS R3010 FPC ISA I
*/
-#define MIPS_R6010 0x04 /* MIPS R6010 FPC ISA II
*/
-#define MIPS_R4010 0x05 /* MIPS R4000/R4400 FPC ISA II
*/
-#define MIPS_R31LSI 0x06 /* LSI Logic derivate ISA I
*/
-#define MIPS_R10010 0x09 /* MIPS R10000/T5 FPU ISA IV
*/
-#define MIPS_R4210 0x0a /* MIPS R4200 FPC (ICE) ISA III
*/
-#define MIPS_UNKF1 0x0b /* unnanounced product cpu ISA III
*/
-#define MIPS_R8000 0x10 /* MIPS R8000 Blackbird/TFP ISA IV
*/
-#define MIPS_R4600 0x20 /* QED R4600 Orion ISA III
*/
-#define MIPS_R3SONY 0x21 /* Sony R3000 based FPU ISA I
*/
-#define MIPS_R3TOSH 0x22 /* Toshiba R3000 based FPU ISA I
*/
-#define MIPS_R5010 0x23 /* MIPS R5000 based FPU ISA IV
*/
-#define MIPS_RM7000 0x27 /* QED RM7000 FPU ISA IV
*/
-#define MIPS_RM5230 0x28 /* QED RM52X0 based FPU ISA IV
*/
-#define MIPS_RM52XX 0x28 /* QED RM52X0 based FPU ISA IV
*/
-#define MIPS_VR5400 0x54 /* NEC Vr5400 FPU ISA IV+
*/
+#endif /* !_LOCORE */
#if defined(_KERNEL) && !defined(_LOCORE)
-struct user;
-
-int Mips_ConfigCache(void);
-void Mips_SyncCache(void);
-void Mips_SyncDCache(vm_offset_t, int);
-void Mips_HitSyncDCache(vm_offset_t, int);
-void Mips_HitSyncSCache(vm_offset_t, int);
-void Mips_IOSyncDCache(vm_offset_t, int, int);
-void Mips_HitInvalidateDCache(vm_offset_t, int);
-void Mips_SyncICache(vm_offset_t, int);
-void Mips_InvalidateICache(vm_offset_t, int);
-
-void wbflush(void);
-
-extern u_int32_t cpu_counter_interval; /* Number of counter ticks/tick */
-extern u_int32_t cpu_counter_last; /* Last compare value loaded */
-extern int num_tlbentries;
extern char btext[];
extern char etext[];
-extern int intr_nesting_level;
-
-#define func_0args_asmmacro(func, in)
\
- __asm __volatile ( "jalr %0" \
- : "=r" (in) /* outputs */ \
- : "r" (func) /* inputs */ \
- : "$31", "$4");
-
-#define func_1args_asmmacro(func, arg0)
\
- __asm __volatile ("move $4, %1;" \
- "jalr %0" \
- : /* outputs */ \
- : "r" (func), "r" (arg0) /* inputs */ \
- : "$31", "$4");
-
-#define func_2args_asmmacro(func, arg0, arg1)
\
- __asm __volatile ("move $4, %1;" \
- "move $5, %2;" \
- "jalr %0" \
- : /* outputs */ \
- : "r" (func), "r" (arg0), "r" (arg1) /* inputs */ \
- : "$31", "$4", "$5");
-
-#define func_3args_asmmacro(func, arg0, arg1, arg2)
\
- __asm __volatile ( "move $4, %1;" \
- "move $5, %2;" \
- "move $6, %3;" \
- "jalr %0" \
- : /* outputs */ \
- : "r" (func), "r" (arg0), "r" (arg1), "r" (arg2) /*
inputs */ \
- : "$31", "$4", "$5", "$6");
-
-/*
- * Enable realtime clock (always enabled).
- */
-#define enablertclock()
-
-/*
- * Are we in an interrupt handler? required by JunOS
- */
-#define IN_INT_HANDLER() \
- (curthread->td_intr_nesting_level != 0 || \
- (curthread->td_pflags & TDP_ITHREAD))
-
-/*
- * Low level access routines to CPU registers
- */
void swi_vm(void *);
void cpu_halt(void);
void cpu_reset(void);
-u_int32_t set_intr_mask(u_int32_t);
-u_int32_t get_intr_mask(void);
-
-#define cpu_spinwait() /* nothing */
-
#endif /* _KERNEL */
#endif /* !_MACHINE_CPU_H_ */
Modified: head/sys/mips/include/md_var.h
==============================================================================
--- head/sys/mips/include/md_var.h Thu Jul 15 01:55:28 2010
(r210099)
+++ head/sys/mips/include/md_var.h Thu Jul 15 01:58:20 2010
(r210100)
@@ -77,4 +77,7 @@ void platform_identify(void);
extern int busdma_swi_pending;
void busdma_swi(void);
+u_int32_t set_intr_mask(u_int32_t);
+u_int32_t get_intr_mask(void);
+
#endif /* !_MACHINE_MD_VAR_H_ */
Modified: head/sys/mips/include/tlb.h
==============================================================================
--- head/sys/mips/include/tlb.h Thu Jul 15 01:55:28 2010 (r210099)
+++ head/sys/mips/include/tlb.h Thu Jul 15 01:58:20 2010 (r210100)
@@ -35,5 +35,6 @@ void tlb_invalidate_all(void);
void tlb_invalidate_all_user(struct pmap *);
void tlb_save(void);
void tlb_update(struct pmap *, vm_offset_t, pt_entry_t);
+extern int num_tlbentries;
#endif /* !_MACHINE_TLB_H_ */
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