Author: nwhitehorn
Date: Mon Oct 4 16:07:48 2010
New Revision: 213407
URL: http://svn.freebsd.org/changeset/base/213407
Log:
Follow exactly the steps in architecture manual for correctly invalidating
TLB entries instead of trying to cut corners.
Modified:
head/sys/powerpc/aim/mmu_oea.c
head/sys/powerpc/aim/mmu_oea64.c
Modified: head/sys/powerpc/aim/mmu_oea.c
==============================================================================
--- head/sys/powerpc/aim/mmu_oea.c Mon Oct 4 16:02:11 2010
(r213406)
+++ head/sys/powerpc/aim/mmu_oea.c Mon Oct 4 16:07:48 2010
(r213407)
@@ -425,9 +425,9 @@ tlbie(vm_offset_t va)
{
mtx_lock_spin(&tlbie_mtx);
+ __asm __volatile("ptesync");
__asm __volatile("tlbie %0" :: "r"(va));
- __asm __volatile("tlbsync");
- powerpc_sync();
+ __asm __volatile("eieio; tlbsync; ptesync");
mtx_unlock_spin(&tlbie_mtx);
}
Modified: head/sys/powerpc/aim/mmu_oea64.c
==============================================================================
--- head/sys/powerpc/aim/mmu_oea64.c Mon Oct 4 16:02:11 2010
(r213406)
+++ head/sys/powerpc/aim/mmu_oea64.c Mon Oct 4 16:07:48 2010
(r213407)
@@ -211,14 +211,14 @@ TLBIE(uint64_t vpn) {
mfmsr %0; \
mr %1, %0; \
insrdi %1,%5,1,0; \
- mtmsrd %1; \
+ mtmsrd %1; isync; \
ptesync; \
\
sld %1,%2,%4; \
or %1,%1,%3; \
tlbie %1; \
\
- mtmsrd %0; \
+ mtmsrd %0; isync; \
eieio; \
tlbsync; \
ptesync;"
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