Author: yongari
Date: Tue Nov 2 23:23:48 2010
New Revision: 214702
URL: http://svn.freebsd.org/changeset/base/214702
Log:
MFC r213411,213464-213465,213468:
r213411:
Enable fix for read DMA FIFO overruns on controllers that have this
fix. Note, we still need workaround for controllers that lacks this
fix and it needs more work in RX BD updating.
Submitted by: davidch
r213464:
Separate common flags into controller specific and PHY related
flags. There should be no functional changes. This change will make
it easy to add more quirk/flags in future.
Reviewed by: davidch
r213465:
Rearrange code a bit to correctly set PHY flags. This change make
it easy to add more newer ASICs.
Obtained from: OpenBSD
r213468:
Fix bge(4) build breakage when BGE_REGISTER_DEBUG is defined.
Modified:
stable/8/sys/dev/bge/if_bge.c
stable/8/sys/dev/bge/if_bgereg.h
stable/8/sys/dev/mii/brgphy.c
Directory Properties:
stable/8/sys/ (props changed)
stable/8/sys/amd64/include/xen/ (props changed)
stable/8/sys/cddl/contrib/opensolaris/ (props changed)
stable/8/sys/contrib/dev/acpica/ (props changed)
stable/8/sys/contrib/pf/ (props changed)
stable/8/sys/dev/xen/xenpci/ (props changed)
Modified: stable/8/sys/dev/bge/if_bge.c
==============================================================================
--- stable/8/sys/dev/bge/if_bge.c Tue Nov 2 23:07:38 2010
(r214701)
+++ stable/8/sys/dev/bge/if_bge.c Tue Nov 2 23:23:48 2010
(r214702)
@@ -1858,6 +1858,19 @@ bge_blockinit(struct bge_softc *sc)
sc->bge_asicrev == BGE_ASICREV_BCM57780)
val |= BGE_RDMAMODE_TSO6_ENABLE;
}
+ if (sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
+ sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
+ sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
+ sc->bge_asicrev == BGE_ASICREV_BCM57780) {
+ /*
+ * Enable fix for read DMA FIFO overruns.
+ * The fix is to limit the number of RX BDs
+ * the hardware would fetch at a fime.
+ */
+ CSR_WRITE_4(sc, BGE_RDMA_RSRVCTRL,
+ CSR_READ_4(sc, BGE_RDMA_RSRVCTRL) |
+ BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
+ }
CSR_WRITE_4(sc, BGE_RDMA_MODE, val);
DELAY(40);
@@ -2497,7 +2510,7 @@ bge_attach(device_t dev)
sc->bge_asicrev != BGE_ASICREV_BCM5906 &&
sc->bge_chipid != BGE_CHIPID_BCM5705_A0 &&
sc->bge_chipid != BGE_CHIPID_BCM5705_A1)
- sc->bge_flags |= BGE_FLAG_WIRESPEED;
+ sc->bge_phy_flags |= BGE_PHY_WIRESPEED;
if (bge_has_eaddr(sc))
sc->bge_flags |= BGE_FLAG_EADDR;
@@ -2534,30 +2547,32 @@ bge_attach(device_t dev)
break;
}
- /* Set various bug flags. */
+ /* Set various PHY bug flags. */
if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 ||
sc->bge_chipid == BGE_CHIPID_BCM5701_B0)
- sc->bge_flags |= BGE_FLAG_CRC_BUG;
+ sc->bge_phy_flags |= BGE_PHY_CRC_BUG;
if (sc->bge_chiprev == BGE_CHIPREV_5703_AX ||
sc->bge_chiprev == BGE_CHIPREV_5704_AX)
- sc->bge_flags |= BGE_FLAG_ADC_BUG;
+ sc->bge_phy_flags |= BGE_PHY_ADC_BUG;
if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0)
- sc->bge_flags |= BGE_FLAG_5704_A0_BUG;
+ sc->bge_phy_flags |= BGE_PHY_5704_A0_BUG;
if (pci_get_subvendor(dev) == DELL_VENDORID)
- sc->bge_flags |= BGE_FLAG_NO_3LED;
- if (pci_get_device(dev) == BCOM_DEVICEID_BCM5755M)
- sc->bge_flags |= BGE_FLAG_ADJUST_TRIM;
- if (BGE_IS_5705_PLUS(sc) &&
- !(sc->bge_flags & BGE_FLAG_ADJUST_TRIM)) {
+ sc->bge_phy_flags |= BGE_PHY_NO_3LED;
+ if ((BGE_IS_5705_PLUS(sc)) &&
+ sc->bge_asicrev != BGE_ASICREV_BCM5906 &&
+ sc->bge_asicrev != BGE_ASICREV_BCM5785 &&
+ sc->bge_asicrev != BGE_ASICREV_BCM57780) {
if (sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
sc->bge_asicrev == BGE_ASICREV_BCM5787) {
if (pci_get_device(dev) != BCOM_DEVICEID_BCM5722 &&
pci_get_device(dev) != BCOM_DEVICEID_BCM5756)
- sc->bge_flags |= BGE_FLAG_JITTER_BUG;
- } else if (sc->bge_asicrev != BGE_ASICREV_BCM5906)
- sc->bge_flags |= BGE_FLAG_BER_BUG;
+ sc->bge_phy_flags |= BGE_PHY_JITTER_BUG;
+ if (pci_get_device(dev) == BCOM_DEVICEID_BCM5755M)
+ sc->bge_phy_flags |= BGE_PHY_ADJUST_TRIM;
+ } else
+ sc->bge_phy_flags |= BGE_PHY_BER_BUG;
}
/*
@@ -5342,7 +5357,7 @@ bge_sysctl_debug_info(SYSCTL_HANDLER_ARG
printf(" - PCI-X Bus\n");
if (sc->bge_flags & BGE_FLAG_PCIE)
printf(" - PCI Express Bus\n");
- if (sc->bge_flags & BGE_FLAG_NO_3LED)
+ if (sc->bge_phy_flags & BGE_PHY_NO_3LED)
printf(" - No 3 LEDs\n");
if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG)
printf(" - RX Alignment Bug\n");
Modified: stable/8/sys/dev/bge/if_bgereg.h
==============================================================================
--- stable/8/sys/dev/bge/if_bgereg.h Tue Nov 2 23:07:38 2010
(r214701)
+++ stable/8/sys/dev/bge/if_bgereg.h Tue Nov 2 23:23:48 2010
(r214702)
@@ -1431,6 +1431,7 @@
*/
#define BGE_RDMA_MODE 0x4800
#define BGE_RDMA_STATUS 0x4804
+#define BGE_RDMA_RSRVCTRL 0x4900
/* Read DMA mode register */
#define BGE_RDMAMODE_RESET 0x00000001
@@ -1462,6 +1463,9 @@
#define BGE_RDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100
#define BGE_RDMASTAT_LOCWRITE_TOOBIG 0x00000200
+/* Read DMA Reserved Control register */
+#define BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX 0x00000004
+
/*
* Write DMA control registers
*/
@@ -2659,29 +2663,30 @@ struct bge_softc {
uint32_t bge_flags;
#define BGE_FLAG_TBI 0x00000001
#define BGE_FLAG_JUMBO 0x00000002
-#define BGE_FLAG_WIRESPEED 0x00000004
#define BGE_FLAG_EADDR 0x00000008
#define BGE_FLAG_MII_SERDES 0x00000010
#define BGE_FLAG_MSI 0x00000100
#define BGE_FLAG_PCIX 0x00000200
#define BGE_FLAG_PCIE 0x00000400
#define BGE_FLAG_TSO 0x00000800
-#define BGE_FLAG_5700_FAMILY 0x00001000
-#define BGE_FLAG_5705_PLUS 0x00002000
-#define BGE_FLAG_5714_FAMILY 0x00004000
-#define BGE_FLAG_575X_PLUS 0x00008000
-#define BGE_FLAG_5755_PLUS 0x00010000
-#define BGE_FLAG_40BIT_BUG 0x00020000
-#define BGE_FLAG_4G_BNDRY_BUG 0x00040000
-#define BGE_FLAG_RX_ALIGNBUG 0x00100000
-#define BGE_FLAG_NO_3LED 0x00200000
-#define BGE_FLAG_ADC_BUG 0x00400000
-#define BGE_FLAG_5704_A0_BUG 0x00800000
-#define BGE_FLAG_JITTER_BUG 0x01000000
-#define BGE_FLAG_BER_BUG 0x02000000
-#define BGE_FLAG_ADJUST_TRIM 0x04000000
-#define BGE_FLAG_CRC_BUG 0x08000000
-#define BGE_FLAG_5788 0x20000000
+#define BGE_FLAG_5700_FAMILY 0x00010000
+#define BGE_FLAG_5705_PLUS 0x00020000
+#define BGE_FLAG_5714_FAMILY 0x00040000
+#define BGE_FLAG_575X_PLUS 0x00080000
+#define BGE_FLAG_5755_PLUS 0x00100000
+#define BGE_FLAG_5788 0x00200000
+#define BGE_FLAG_40BIT_BUG 0x01000000
+#define BGE_FLAG_4G_BNDRY_BUG 0x02000000
+#define BGE_FLAG_RX_ALIGNBUG 0x04000000
+ uint32_t bge_phy_flags;
+#define BGE_PHY_WIRESPEED 0x00000001
+#define BGE_PHY_ADC_BUG 0x00000002
+#define BGE_PHY_5704_A0_BUG 0x00000004
+#define BGE_PHY_JITTER_BUG 0x00000008
+#define BGE_PHY_BER_BUG 0x00000010
+#define BGE_PHY_ADJUST_TRIM 0x00000020
+#define BGE_PHY_CRC_BUG 0x00000040
+#define BGE_PHY_NO_3LED 0x00000080
uint32_t bge_chipid;
uint32_t bge_asicrev;
uint32_t bge_chiprev;
Modified: stable/8/sys/dev/mii/brgphy.c
==============================================================================
--- stable/8/sys/dev/mii/brgphy.c Tue Nov 2 23:07:38 2010
(r214701)
+++ stable/8/sys/dev/mii/brgphy.c Tue Nov 2 23:23:48 2010
(r214702)
@@ -1025,26 +1025,26 @@ brgphy_reset(struct mii_softc *sc)
/* Handle any bge (NetXtreme/NetLink) workarounds. */
if (bge_sc) {
/* Fix up various bugs */
- if (bge_sc->bge_flags & BGE_FLAG_5704_A0_BUG)
+ if (bge_sc->bge_phy_flags & BGE_PHY_5704_A0_BUG)
brgphy_fixup_5704_a0_bug(sc);
- if (bge_sc->bge_flags & BGE_FLAG_ADC_BUG)
+ if (bge_sc->bge_phy_flags & BGE_PHY_ADC_BUG)
brgphy_fixup_adc_bug(sc);
- if (bge_sc->bge_flags & BGE_FLAG_ADJUST_TRIM)
+ if (bge_sc->bge_phy_flags & BGE_PHY_ADJUST_TRIM)
brgphy_fixup_adjust_trim(sc);
- if (bge_sc->bge_flags & BGE_FLAG_BER_BUG)
+ if (bge_sc->bge_phy_flags & BGE_PHY_BER_BUG)
brgphy_fixup_ber_bug(sc);
- if (bge_sc->bge_flags & BGE_FLAG_CRC_BUG)
+ if (bge_sc->bge_phy_flags & BGE_PHY_CRC_BUG)
brgphy_fixup_crc_bug(sc);
- if (bge_sc->bge_flags & BGE_FLAG_JITTER_BUG)
+ if (bge_sc->bge_phy_flags & BGE_PHY_JITTER_BUG)
brgphy_fixup_jitter_bug(sc);
brgphy_jumbo_settings(sc, ifp->if_mtu);
- if (bge_sc->bge_flags & BGE_FLAG_WIRESPEED)
+ if (bge_sc->bge_phy_flags & BGE_PHY_WIRESPEED)
brgphy_ethernet_wirespeed(sc);
/* Enable Link LED on Dell boxes */
- if (bge_sc->bge_flags & BGE_FLAG_NO_3LED) {
+ if (bge_sc->bge_phy_flags & BGE_PHY_NO_3LED) {
PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL,
PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL) &
~BRGPHY_PHY_EXTCTL_3_LED);
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