Author: adrian
Date: Fri Mar 11 11:58:54 2011
New Revision: 219481
URL: http://svn.freebsd.org/changeset/base/219481
Log:
Port over the AR9285 PA calibration and initial calibration code from
Linux ath9k.
The ath9k ar9002_hw_init_cal() isn't entirely clear about what
is supposed to be called for what chipsets, so I'm ignoring the
rest of it and just porting the AR9285 init cal path as-is and
leaving the rest alone. Subsequent commits may also tidy up the
Merlin (AR9285) and other chipset support.
Obtained from: Linux ath9k
Added:
head/sys/dev/ath/ath_hal/ar9002/ar9285_cal.c (contents, props changed)
head/sys/dev/ath/ath_hal/ar9002/ar9285_cal.h (contents, props changed)
head/sys/dev/ath/ath_hal/ar9002/ar9285phy.h (contents, props changed)
Modified:
head/sys/conf/files
head/sys/dev/ath/ath_hal/ar9002/ar9285.h
head/sys/dev/ath/ath_hal/ar9002/ar9285_attach.c
head/sys/modules/ath/Makefile
Modified: head/sys/conf/files
==============================================================================
--- head/sys/conf/files Fri Mar 11 11:35:36 2011 (r219480)
+++ head/sys/conf/files Fri Mar 11 11:58:54 2011 (r219481)
@@ -767,6 +767,8 @@ dev/ath/ath_hal/ar9002/ar9285_attach.c o
compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal"
dev/ath/ath_hal/ar9002/ar9285_reset.c optional ath_hal | ath_ar9285 \
compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal"
+dev/ath/ath_hal/ar9002/ar9285_cal.c optional ath_hal | ath_ar9285 \
+ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal"
# rf backends
dev/ath/ath_hal/ar5212/ar2316.c optional ath_rf2316 \
compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal"
Modified: head/sys/dev/ath/ath_hal/ar9002/ar9285.h
==============================================================================
--- head/sys/dev/ath/ath_hal/ar9002/ar9285.h Fri Mar 11 11:35:36 2011
(r219480)
+++ head/sys/dev/ath/ath_hal/ar9002/ar9285.h Fri Mar 11 11:58:54 2011
(r219481)
@@ -25,6 +25,12 @@ struct ath_hal_9285 {
HAL_INI_ARRAY ah_ini_txgain;
HAL_INI_ARRAY ah_ini_rxgain;
+
+ struct {
+ int32_t prev_offset; /* Previous value of PA offset value */
+ int8_t max_skipcount; /* Max No. of times PACAL can be
skipped */
+ int8_t skipcount; /* No. of times the PACAL to be skipped
*/
+ } pacal_info;
};
#define AH9285(_ah) ((struct ath_hal_9285 *)(_ah))
Modified: head/sys/dev/ath/ath_hal/ar9002/ar9285_attach.c
==============================================================================
--- head/sys/dev/ath/ath_hal/ar9002/ar9285_attach.c Fri Mar 11 11:35:36
2011 (r219480)
+++ head/sys/dev/ath/ath_hal/ar9002/ar9285_attach.c Fri Mar 11 11:58:54
2011 (r219481)
@@ -33,6 +33,8 @@
#include "ar9002/ar9285v2.ini"
#include "ar9002/ar9280v2.ini" /* XXX ini for tx/rx gain */
+#include "ar9002/ar9285_cal.h"
+
static const HAL_PERCAL_DATA ar9280_iq_cal = { /* single sample */
.calName = "IQ", .calType = IQ_MISMATCH_CAL,
.calNumSamples = MIN_CAL_SAMPLES,
@@ -118,6 +120,10 @@ ar9285Attach(uint16_t devid, HAL_SOFTC s
AH5416(ah)->ah_cal.adcDcCalInitData.calData = &ar9280_adc_init_dc_cal;
AH5416(ah)->ah_cal.suppCals = ADC_GAIN_CAL | ADC_DC_CAL |
IQ_MISMATCH_CAL;
+ if (AR_SREV_KITE_12_OR_LATER(ah))
+ AH5416(ah)->ah_cal_initcal = ar9285InitCalHardware;
+ AH5416(ah)->ah_cal_pacal = ar9002_hw_pa_cal;
+
AH5416(ah)->ah_spurMitigate = ar9280SpurMitigate;
AH5416(ah)->ah_writeIni = ar9285WriteIni;
AH5416(ah)->ah_rx_chainmask = AR9285_DEFAULT_RXCHAINMASK;
Added: head/sys/dev/ath/ath_hal/ar9002/ar9285_cal.c
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ head/sys/dev/ath/ath_hal/ar9002/ar9285_cal.c Fri Mar 11 11:58:54
2011 (r219481)
@@ -0,0 +1,269 @@
+/*
+ * Copyright (c) 2008-2010 Atheros Communications Inc.
+ * Copyright (c) 2011 Adrian Chadd, Xenion Pty Ltd.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+#include "opt_ah.h"
+#include "ah.h"
+#include "ah_internal.h"
+
+#include "ah_eeprom_v4k.h"
+
+#include "ar9002/ar9285.h"
+#include "ar5416/ar5416reg.h"
+#include "ar5416/ar5416phy.h"
+#include "ar9002/ar9002phy.h"
+#include "ar9002/ar9285phy.h"
+
+#include "ar9002/ar9285_cal.h"
+
+#define AR9285_CLCAL_REDO_THRESH 1
+#define MAX_PACAL_SKIPCOUNT 8
+
+#define N(a) (sizeof (a) / sizeof (a[0]))
+
+static void
+ar9285_hw_pa_cal(struct ath_hal *ah, HAL_BOOL is_reset)
+{
+ uint32_t regVal;
+ int i, offset, offs_6_1, offs_0;
+ uint32_t ccomp_org, reg_field;
+ uint32_t regList[][2] = {
+ { 0x786c, 0 },
+ { 0x7854, 0 },
+ { 0x7820, 0 },
+ { 0x7824, 0 },
+ { 0x7868, 0 },
+ { 0x783c, 0 },
+ { 0x7838, 0 },
+ };
+
+ HALDEBUG(ah, HAL_DEBUG_PERCAL, "Running PA Calibration\n");
+
+ /* PA CAL is not needed for high power solution */
+ if (ath_hal_eepromGet(ah, AR_EEP_TXGAIN_TYPE, AH_NULL) ==
+ AR5416_EEP_TXGAIN_HIGH_POWER)
+ return;
+
+ for (i = 0; i < N(regList); i++)
+ regList[i][1] = OS_REG_READ(ah, regList[i][0]);
+
+ regVal = OS_REG_READ(ah, 0x7834);
+ regVal &= (~(0x1));
+ OS_REG_WRITE(ah, 0x7834, regVal);
+ regVal = OS_REG_READ(ah, 0x9808);
+ regVal |= (0x1 << 27);
+ OS_REG_WRITE(ah, 0x9808, regVal);
+
+ OS_REG_RMW_FIELD(ah, AR9285_AN_TOP3, AR9285_AN_TOP3_PWDDAC, 1);
+ OS_REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDRXTXBB1, 1);
+ OS_REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDV2I, 1);
+ OS_REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDDACIF, 1);
+ OS_REG_RMW_FIELD(ah, AR9285_AN_RF2G2, AR9285_AN_RF2G2_OFFCAL, 0);
+ OS_REG_RMW_FIELD(ah, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PWDDB, 0);
+ OS_REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_ENPACAL, 0);
+ OS_REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV1, 0);
+ OS_REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV2, 0);
+ OS_REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPAOUT, 0);
+ OS_REG_RMW_FIELD(ah, AR9285_AN_RF2G8, AR9285_AN_RF2G8_PADRVGN2TAB0, 7);
+ OS_REG_RMW_FIELD(ah, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PADRVGN2TAB0, 0);
+ ccomp_org = MS(OS_REG_READ(ah, AR9285_AN_RF2G6), AR9285_AN_RF2G6_CCOMP);
+ OS_REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_CCOMP, 0xf);
+
+ OS_REG_WRITE(ah, AR9285_AN_TOP2, 0xca0358a0);
+ OS_DELAY(30);
+ OS_REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_OFFS, 0);
+ OS_REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, 0);
+
+ for (i = 6; i > 0; i--) {
+ regVal = OS_REG_READ(ah, 0x7834);
+ regVal |= (1 << (19 + i));
+ OS_REG_WRITE(ah, 0x7834, regVal);
+ OS_DELAY(1);
+ regVal = OS_REG_READ(ah, 0x7834);
+ regVal &= (~(0x1 << (19 + i)));
+ reg_field = MS(OS_REG_READ(ah, 0x7840),
AR9285_AN_RXTXBB1_SPARE9);
+ regVal |= (reg_field << (19 + i));
+ OS_REG_WRITE(ah, 0x7834, regVal);
+ }
+
+ OS_REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, 1);
+ OS_DELAY(1);
+ reg_field = MS(OS_REG_READ(ah, AR9285_AN_RF2G9),
AR9285_AN_RXTXBB1_SPARE9);
+ OS_REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP,
reg_field);
+ offs_6_1 = MS(OS_REG_READ(ah, AR9285_AN_RF2G6), AR9285_AN_RF2G6_OFFS);
+ offs_0 = MS(OS_REG_READ(ah, AR9285_AN_RF2G3),
AR9285_AN_RF2G3_PDVCCOMP);
+
+ offset = (offs_6_1<<1) | offs_0;
+ offset = offset - 0;
+ offs_6_1 = offset>>1;
+ offs_0 = offset & 1;
+
+ if ((!is_reset) && (AH9285(ah)->pacal_info.prev_offset == offset)) {
+ if (AH9285(ah)->pacal_info.max_skipcount < MAX_PACAL_SKIPCOUNT)
+ AH9285(ah)->pacal_info.max_skipcount =
+ 2 * AH9285(ah)->pacal_info.max_skipcount;
+ AH9285(ah)->pacal_info.skipcount =
AH9285(ah)->pacal_info.max_skipcount;
+ } else {
+ AH9285(ah)->pacal_info.max_skipcount = 1;
+ AH9285(ah)->pacal_info.skipcount = 0;
+ AH9285(ah)->pacal_info.prev_offset = offset;
+ }
+
+ OS_REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_OFFS, offs_6_1);
+ OS_REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, offs_0);
+
+ regVal = OS_REG_READ(ah, 0x7834);
+ regVal |= 0x1;
+ OS_REG_WRITE(ah, 0x7834, regVal);
+ regVal = OS_REG_READ(ah, 0x9808);
+ regVal &= (~(0x1 << 27));
+ OS_REG_WRITE(ah, 0x9808, regVal);
+
+ for (i = 0; i < N(regList); i++)
+ OS_REG_WRITE(ah, regList[i][0], regList[i][1]);
+
+ OS_REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_CCOMP, ccomp_org);
+}
+
+void
+ar9002_hw_pa_cal(struct ath_hal *ah, HAL_BOOL is_reset)
+{
+ if (AR_SREV_KITE_12_OR_LATER(ah)) {
+ if (is_reset || !AH9285(ah)->pacal_info.skipcount)
+ ar9285_hw_pa_cal(ah, is_reset);
+ else
+ AH9285(ah)->pacal_info.skipcount--;
+ }
+}
+
+/* Carrier leakage Calibration fix */
+static HAL_BOOL
+ar9285_hw_cl_cal(struct ath_hal *ah, const struct ieee80211_channel *chan)
+{
+ OS_REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
+ if (IEEE80211_IS_CHAN_HT20(chan)) {
+ OS_REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL,
AR_PHY_PARALLEL_CAL_ENABLE);
+ OS_REG_SET_BIT(ah, AR_PHY_TURBO, AR_PHY_FC_DYN2040_EN);
+ OS_REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
+ AR_PHY_AGC_CONTROL_FLTR_CAL);
+ OS_REG_CLR_BIT(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_CAL_ENABLE);
+ OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL);
+ if (!ath_hal_wait(ah, AR_PHY_AGC_CONTROL,
+ AR_PHY_AGC_CONTROL_CAL, 0)) {
+ HALDEBUG(ah, HAL_DEBUG_PERCAL,
+ "offset calibration failed to complete in 1ms;
noisy environment?\n");
+ return AH_FALSE;
+ }
+ OS_REG_CLR_BIT(ah, AR_PHY_TURBO, AR_PHY_FC_DYN2040_EN);
+ OS_REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL,
AR_PHY_PARALLEL_CAL_ENABLE);
+ OS_REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
+ }
+ OS_REG_CLR_BIT(ah, AR_PHY_ADC_CTL, AR_PHY_ADC_CTL_OFF_PWDADC);
+ OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_FLTR_CAL);
+ OS_REG_SET_BIT(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_CAL_ENABLE);
+ OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL);
+ if (!ath_hal_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL,
+ 0)) {
+ HALDEBUG(ah, HAL_DEBUG_PERCAL,
+ "offset calibration failed to complete in 1ms; noisy
environment?\n");
+ return AH_FALSE;
+ }
+
+ OS_REG_SET_BIT(ah, AR_PHY_ADC_CTL, AR_PHY_ADC_CTL_OFF_PWDADC);
+ OS_REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
+ OS_REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_FLTR_CAL);
+
+ return AH_TRUE;
+}
+
+static HAL_BOOL
+ar9285_hw_clc(struct ath_hal *ah, const struct ieee80211_channel *chan)
+{
+ int i;
+ uint32_t txgain_max;
+ uint32_t clc_gain, gain_mask = 0, clc_num = 0;
+ uint32_t reg_clc_I0, reg_clc_Q0;
+ uint32_t i0_num = 0;
+ uint32_t q0_num = 0;
+ uint32_t total_num = 0;
+ uint32_t reg_rf2g5_org;
+ HAL_BOOL retv = AH_TRUE;
+
+ if (!(ar9285_hw_cl_cal(ah, chan)))
+ return AH_FALSE;
+
+ txgain_max = MS(OS_REG_READ(ah, AR_PHY_TX_PWRCTRL7),
+ AR_PHY_TX_PWRCTRL_TX_GAIN_TAB_MAX);
+
+ for (i = 0; i < (txgain_max+1); i++) {
+ clc_gain = (OS_REG_READ(ah, (AR_PHY_TX_GAIN_TBL1+(i<<2))) &
+ AR_PHY_TX_GAIN_CLC) >> AR_PHY_TX_GAIN_CLC_S;
+ if (!(gain_mask & (1 << clc_gain))) {
+ gain_mask |= (1 << clc_gain);
+ clc_num++;
+ }
+ }
+
+ for (i = 0; i < clc_num; i++) {
+ reg_clc_I0 = (OS_REG_READ(ah, (AR_PHY_CLC_TBL1 + (i << 2)))
+ & AR_PHY_CLC_I0) >> AR_PHY_CLC_I0_S;
+ reg_clc_Q0 = (OS_REG_READ(ah, (AR_PHY_CLC_TBL1 + (i << 2)))
+ & AR_PHY_CLC_Q0) >> AR_PHY_CLC_Q0_S;
+ if (reg_clc_I0 == 0)
+ i0_num++;
+
+ if (reg_clc_Q0 == 0)
+ q0_num++;
+ }
+ total_num = i0_num + q0_num;
+ if (total_num > AR9285_CLCAL_REDO_THRESH) {
+ reg_rf2g5_org = OS_REG_READ(ah, AR9285_RF2G5);
+ if (AR_SREV_9285E_20(ah)) {
+ OS_REG_WRITE(ah, AR9285_RF2G5,
+ (reg_rf2g5_org & AR9285_RF2G5_IC50TX) |
+ AR9285_RF2G5_IC50TX_XE_SET);
+ } else {
+ OS_REG_WRITE(ah, AR9285_RF2G5,
+ (reg_rf2g5_org & AR9285_RF2G5_IC50TX) |
+ AR9285_RF2G5_IC50TX_SET);
+ }
+ retv = ar9285_hw_cl_cal(ah, chan);
+ OS_REG_WRITE(ah, AR9285_RF2G5, reg_rf2g5_org);
+ }
+ return retv;
+}
+
+HAL_BOOL
+ar9285InitCalHardware(struct ath_hal *ah,
+ const struct ieee80211_channel *chan)
+{
+ if (! ar9285_hw_clc(ah, chan))
+ return AH_FALSE;
+
+ ar9285_hw_pa_cal(ah, AH_TRUE);
+
+ return AH_TRUE;
+}
Added: head/sys/dev/ath/ath_hal/ar9002/ar9285_cal.h
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ head/sys/dev/ath/ath_hal/ar9002/ar9285_cal.h Fri Mar 11 11:58:54
2011 (r219481)
@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2008-2010 Atheros Communications Inc.
+ * Copyright (c) 2011 Adrian Chadd, Xenion Pty Ltd.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+#ifndef __AR9285_CAL_H__
+#define __AR9285_CAL_H__
+
+extern void ar9002_hw_pa_cal(struct ath_hal *ah, HAL_BOOL is_reset);
+extern HAL_BOOL ar9285InitCalHardware(struct ath_hal *ah, const struct
ieee80211_channel *chan);
+
+#endif
Added: head/sys/dev/ath/ath_hal/ar9002/ar9285phy.h
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ head/sys/dev/ath/ath_hal/ar9002/ar9285phy.h Fri Mar 11 11:58:54 2011
(r219481)
@@ -0,0 +1,130 @@
+/*
+ * Copyright (c) 2008-2010 Atheros Communications Inc.
+ * Copyright (c) 2010-2011 Adrian Chadd, Xenion Pty Ltd.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+#ifndef __ATH_AR9285PHY_H__
+#define __ATH_AR9285PHY_H__
+
+#define AR9285_AN_RF2G1 0x7820
+#define AR9285_AN_RF2G1_ENPACAL 0x00000800
+#define AR9285_AN_RF2G1_ENPACAL_S 11
+#define AR9285_AN_RF2G1_PDPADRV1 0x02000000
+#define AR9285_AN_RF2G1_PDPADRV1_S 25
+#define AR9285_AN_RF2G1_PDPADRV2 0x01000000
+#define AR9285_AN_RF2G1_PDPADRV2_S 24
+#define AR9285_AN_RF2G1_PDPAOUT 0x00800000
+#define AR9285_AN_RF2G1_PDPAOUT_S 23
+
+#define AR9285_AN_RF2G2 0x7824
+#define AR9285_AN_RF2G2_OFFCAL 0x00001000
+#define AR9285_AN_RF2G2_OFFCAL_S 12
+
+#define AR9285_AN_RF2G3 0x7828
+#define AR9285_AN_RF2G3_PDVCCOMP 0x02000000
+#define AR9285_AN_RF2G3_PDVCCOMP_S 25
+#define AR9285_AN_RF2G3_OB_0 0x00E00000
+#define AR9285_AN_RF2G3_OB_0_S 21
+#define AR9285_AN_RF2G3_OB_1 0x001C0000
+#define AR9285_AN_RF2G3_OB_1_S 18
+#define AR9285_AN_RF2G3_OB_2 0x00038000
+#define AR9285_AN_RF2G3_OB_2_S 15
+#define AR9285_AN_RF2G3_OB_3 0x00007000
+#define AR9285_AN_RF2G3_OB_3_S 12
+#define AR9285_AN_RF2G3_OB_4 0x00000E00
+#define AR9285_AN_RF2G3_OB_4_S 9
+
+#define AR9285_AN_RF2G3_DB1_0 0x000001C0
+#define AR9285_AN_RF2G3_DB1_0_S 6
+#define AR9285_AN_RF2G3_DB1_1 0x00000038
+#define AR9285_AN_RF2G3_DB1_1_S 3
+#define AR9285_AN_RF2G3_DB1_2 0x00000007
+#define AR9285_AN_RF2G3_DB1_2_S 0
+
+#define AR9285_AN_RF2G4 0x782C
+#define AR9285_AN_RF2G4_DB1_3 0xE0000000
+#define AR9285_AN_RF2G4_DB1_3_S 29
+#define AR9285_AN_RF2G4_DB1_4 0x1C000000
+#define AR9285_AN_RF2G4_DB1_4_S 26
+
+#define AR9285_AN_RF2G4_DB2_0 0x03800000
+#define AR9285_AN_RF2G4_DB2_0_S 23
+#define AR9285_AN_RF2G4_DB2_1 0x00700000
+#define AR9285_AN_RF2G4_DB2_1_S 20
+#define AR9285_AN_RF2G4_DB2_2 0x000E0000
+#define AR9285_AN_RF2G4_DB2_2_S 17
+#define AR9285_AN_RF2G4_DB2_3 0x0001C000
+#define AR9285_AN_RF2G4_DB2_3_S 14
+#define AR9285_AN_RF2G4_DB2_4 0x00003800
+#define AR9285_AN_RF2G4_DB2_4_S 11
+
+#define AR9285_RF2G5 0x7830
+#define AR9285_RF2G5_IC50TX 0xfffff8ff
+#define AR9285_RF2G5_IC50TX_SET 0x00000400
+#define AR9285_RF2G5_IC50TX_XE_SET 0x00000500
+#define AR9285_RF2G5_IC50TX_CLEAR 0x00000700
+#define AR9285_RF2G5_IC50TX_CLEAR_S 8
+
+#define AR_PHY_TX_PWRCTRL_TX_GAIN_TAB_MAX 0x0007E000
+#define AR_PHY_TX_PWRCTRL_TX_GAIN_TAB_MAX_S 13
+#define AR_PHY_TX_GAIN_CLC 0x0000001E
+#define AR_PHY_TX_GAIN_CLC_S 1
+#define AR_PHY_TX_GAIN 0x0007F000
+#define AR_PHY_TX_GAIN_S 12
+
+#define AR_PHY_CLC_TBL1 0xa35c
+#define AR_PHY_CLC_I0 0x07ff0000
+#define AR_PHY_CLC_I0_S 16
+#define AR_PHY_CLC_Q0 0x0000ffd0
+#define AR_PHY_CLC_Q0_S 5
+
+#define AR_PHY_MULTICHAIN_GAIN_CTL 0x99ac
+#define AR_PHY_9285_FAST_DIV_BIAS 0x00007E00
+#define AR_PHY_9285_FAST_DIV_BIAS_S 9
+#define AR_PHY_9285_ANT_DIV_CTL_ALL 0x7f000000
+#define AR_PHY_9285_ANT_DIV_CTL 0x01000000
+#define AR_PHY_9285_ANT_DIV_CTL_S 24
+#define AR_PHY_9285_ANT_DIV_ALT_LNACONF 0x06000000
+#define AR_PHY_9285_ANT_DIV_ALT_LNACONF_S 25
+#define AR_PHY_9285_ANT_DIV_MAIN_LNACONF 0x18000000
+#define AR_PHY_9285_ANT_DIV_MAIN_LNACONF_S 27
+#define AR_PHY_9285_ANT_DIV_ALT_GAINTB 0x20000000
+#define AR_PHY_9285_ANT_DIV_ALT_GAINTB_S 29
+#define AR_PHY_9285_ANT_DIV_MAIN_GAINTB 0x40000000
+#define AR_PHY_9285_ANT_DIV_MAIN_GAINTB_S 30
+#define AR_PHY_9285_ANT_DIV_LNA1 2
+#define AR_PHY_9285_ANT_DIV_LNA2 1
+#define AR_PHY_9285_ANT_DIV_LNA1_PLUS_LNA2 3
+#define AR_PHY_9285_ANT_DIV_LNA1_MINUS_LNA2 0
+#define AR_PHY_9285_ANT_DIV_GAINTB_0 0
+#define AR_PHY_9285_ANT_DIV_GAINTB_1 1
+
+/* for AR_PHY_CCK_DETECT */
+#define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME 0x00001FC0
+#define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME_S 6
+#define AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV 0x2000
+#define AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV_S 13
+
+#endif
Modified: head/sys/modules/ath/Makefile
==============================================================================
--- head/sys/modules/ath/Makefile Fri Mar 11 11:35:36 2011
(r219480)
+++ head/sys/modules/ath/Makefile Fri Mar 11 11:58:54 2011
(r219481)
@@ -98,7 +98,7 @@ SRCS+= ar9160_attach.c
.PATH: ${.CURDIR}/../../dev/ath/ath_hal/ar9002
SRCS+= ar9280.c ar9280_attach.c ar9280_olc.c
-SRCS+= ar9285.c ar9285_reset.c ar9285_attach.c
+SRCS+= ar9285.c ar9285_reset.c ar9285_attach.c ar9285_cal.c
# NB: rate control is bound to the driver by symbol names so only pick one
.if ${ATH_RATE} == "sample"
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