Author: avg
Date: Fri Mar 11 14:55:23 2011
New Revision: 219487
URL: http://svn.freebsd.org/changeset/base/219487
Log:
MFC r215523: specialreg.h: add AMD-specific "Hardware Configuration
Register" MSR
Modified:
stable/7/sys/amd64/include/specialreg.h
stable/7/sys/i386/i386/initcpu.c
stable/7/sys/i386/include/specialreg.h
Directory Properties:
stable/7/sys/ (props changed)
stable/7/sys/cddl/contrib/opensolaris/ (props changed)
stable/7/sys/contrib/dev/acpica/ (props changed)
stable/7/sys/contrib/pf/ (props changed)
Modified: stable/7/sys/amd64/include/specialreg.h
==============================================================================
--- stable/7/sys/amd64/include/specialreg.h Fri Mar 11 14:53:34 2011
(r219486)
+++ stable/7/sys/amd64/include/specialreg.h Fri Mar 11 14:55:23 2011
(r219487)
@@ -494,6 +494,7 @@
#define MSR_PERFCTR2 0xc0010006
#define MSR_PERFCTR3 0xc0010007
#define MSR_SYSCFG 0xc0010010
+#define MSR_HWCR 0xc0010015
#define MSR_IORRBASE0 0xc0010016
#define MSR_IORRMASK0 0xc0010017
#define MSR_IORRBASE1 0xc0010018
Modified: stable/7/sys/i386/i386/initcpu.c
==============================================================================
--- stable/7/sys/i386/i386/initcpu.c Fri Mar 11 14:53:34 2011
(r219486)
+++ stable/7/sys/i386/i386/initcpu.c Fri Mar 11 14:55:23 2011
(r219487)
@@ -680,7 +680,7 @@ initializecpu(void)
(cpu_id & ~0xf) == 0x670 ||
(cpu_id & ~0xf) == 0x680)) {
u_int regs[4];
- wrmsr(0xC0010015, rdmsr(0xC0010015) & ~0x08000);
+ wrmsr(MSR_HWCR, rdmsr(MSR_HWCR) & ~0x08000);
do_cpuid(1, regs);
cpu_feature = regs[3];
}
Modified: stable/7/sys/i386/include/specialreg.h
==============================================================================
--- stable/7/sys/i386/include/specialreg.h Fri Mar 11 14:53:34 2011
(r219486)
+++ stable/7/sys/i386/include/specialreg.h Fri Mar 11 14:55:23 2011
(r219487)
@@ -544,7 +544,8 @@
#define AMD_WT_ALLOC_FRE 0x10000 /* fixed (A0000-FFFFF) range
enable */
/* AMD64 MSR's */
-#define MSR_EFER 0xc0000080 /* extended features */
+#define MSR_EFER 0xc0000080 /* extended features */
+#define MSR_HWCR 0xc0010015
#define MSR_K8_UCODE_UPDATE 0xc0010020 /* update microcode */
#define MSR_MC0_CTL_MASK 0xc0010044
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