Author: adrian
Date: Wed Apr 13 04:40:59 2011
New Revision: 220590
URL: http://svn.freebsd.org/changeset/base/220590
Log:
Port over a TX gain fix from ath9k specific to the AR9285 (Kite) and AR9271.
Note: this HAL currently only supports the AR9285.
From Linux ath9k:
The problem is that when the attenuation is increased,
the rate will start to drop from MCS7 -> MCS6, and finally
will see MCS1 -> CCK_11Mbps. When the rate is changed b/w
CCK and OFDM, it will use register desired_scale to calculate
how much tx gain need to change.
The output power with the same tx gain for CCK and OFDM modulated
signals are different. This difference is constant for AR9280
but not AR9285/AR9271. It has different PA architecture
a constant. So it should be calibrated against this PA
characteristic.
The driver has to read the calibrated values from EEPROM and set
the tx power registers accordingly.
Modified:
head/sys/dev/ath/ath_hal/ar9002/ar9002phy.h
head/sys/dev/ath/ath_hal/ar9002/ar9285_reset.c
Modified: head/sys/dev/ath/ath_hal/ar9002/ar9002phy.h
==============================================================================
--- head/sys/dev/ath/ath_hal/ar9002/ar9002phy.h Wed Apr 13 03:05:42 2011
(r220589)
+++ head/sys/dev/ath/ath_hal/ar9002/ar9002phy.h Wed Apr 13 04:40:59 2011
(r220590)
@@ -42,9 +42,16 @@
#define AR_PHY_TX_PWRCTRL_INIT_TX_GAIN 0x01F80000
#define AR_PHY_TX_PWRCTRL_INIT_TX_GAIN_S 19
+#define AR_PHY_TX_PWRCTRL8 0xa278
+#define AR_PHY_TX_PWRCTRL10 0xa394
#define AR_PHY_TX_GAIN_TBL1 0xa300
#define AR_PHY_TX_GAIN 0x0007F000
#define AR_PHY_TX_GAIN_S 12
+#define AR_PHY_CH0_TX_PWRCTRL11 0xa398
+#define AR_PHY_CH1_TX_PWRCTRL11 0xb398
+#define AR_PHY_CH0_TX_PWRCTRL12 0xa3dc
+#define AR_PHY_CH0_TX_PWRCTRL13 0xa3e0
+
#endif
Modified: head/sys/dev/ath/ath_hal/ar9002/ar9285_reset.c
==============================================================================
--- head/sys/dev/ath/ath_hal/ar9002/ar9285_reset.c Wed Apr 13 03:05:42
2011 (r220589)
+++ head/sys/dev/ath/ath_hal/ar9002/ar9285_reset.c Wed Apr 13 04:40:59
2011 (r220590)
@@ -35,7 +35,7 @@
#include "ar5416/ar5416.h"
#include "ar5416/ar5416reg.h"
#include "ar5416/ar5416phy.h"
-
+#include "ar9002/ar9002phy.h"
#include "ar9002/ar9285phy.h"
/* Eeprom versioning macros. Returns true if the version is equal or newer
than the ver specified */
@@ -415,6 +415,42 @@ ar9285SetBoardValues(struct ath_hal *ah,
AR_PHY_SETTLING_SWITCH, pModal->swSettleHt40);
}
+ /*
+ * Program the CCK TX gain factor appropriately if needed.
+ * The AR9285/AR9271 has a non-constant PA tx gain behaviour
+ * for CCK versus OFDM rates; other chips deal with this
+ * differently.
+ *
+ * The mask/shift/multiply hackery is done so place the same
+ * value (bb_desired_scale) into multiple 5-bit fields.
+ * For example, AR_PHY_TX_PWRCTRL9 has bb_desired_scale written
+ * to three fields: (0..4), (5..9) and (10..14).
+ */
+ if (AR_SREV_9271(ah) || AR_SREV_KITE(ah)) {
+ uint8_t bb_desired_scale = (pModal->bb_scale_smrt_antenna &
EEP_4K_BB_DESIRED_SCALE_MASK);
+ if ((eep->baseEepHeader.txGainType == 0) && (bb_desired_scale
!= 0)) {
+ uint32_t pwrctrl, mask, clr;
+
+ mask = (1<<0) | (1<<5) | (1<<10) | (1<<15) | (1<<20) |
(1<<25);
+ pwrctrl = mask * bb_desired_scale;
+ clr = mask * 0x1f;
+ OS_REG_RMW(ah, AR_PHY_TX_PWRCTRL8, pwrctrl, clr);
+ OS_REG_RMW(ah, AR_PHY_TX_PWRCTRL10, pwrctrl, clr);
+ OS_REG_RMW(ah, AR_PHY_CH0_TX_PWRCTRL12, pwrctrl, clr);
+
+ mask = (1<<0) | (1<<5) | (1<<15);
+ pwrctrl = mask * bb_desired_scale;
+ clr = mask * 0x1f;
+ OS_REG_RMW(ah, AR_PHY_TX_PWRCTRL9, pwrctrl, clr);
+
+ mask = (1<<0) | (1<<5);
+ pwrctrl = mask * bb_desired_scale;
+ clr = mask * 0x1f;
+ OS_REG_RMW(ah, AR_PHY_CH0_TX_PWRCTRL11, pwrctrl, clr);
+ OS_REG_RMW(ah, AR_PHY_CH0_TX_PWRCTRL13, pwrctrl, clr);
+ }
+ }
+
return AH_TRUE;
}
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