Author: adrian
Date: Thu May 12 03:25:24 2011
New Revision: 221801
URL: http://svn.freebsd.org/changeset/base/221801
Log:
Fix the half/quater rate PLL setup for AR5416, AR9160 and
(beta?) AR9280 chips.
Note: This doesn't "fix" half/quarter rate support for these
chips; it merely fixes an oversight.
Obtained from: Atheros
Modified:
head/sys/dev/ath/ath_hal/ar5416/ar5416_reset.c
Modified: head/sys/dev/ath/ath_hal/ar5416/ar5416_reset.c
==============================================================================
--- head/sys/dev/ath/ath_hal/ar5416/ar5416_reset.c Thu May 12 03:15:21
2011 (r221800)
+++ head/sys/dev/ath/ath_hal/ar5416/ar5416_reset.c Thu May 12 03:25:24
2011 (r221801)
@@ -1389,10 +1389,12 @@ ar5416InitPLL(struct ath_hal *ah, const
pll |= SM(0x1, AR_RTC_SOWL_PLL_CLKSEL);
else if (IEEE80211_IS_CHAN_QUARTER(chan))
pll |= SM(0x2, AR_RTC_SOWL_PLL_CLKSEL);
- else if (IEEE80211_IS_CHAN_5GHZ(chan))
+
+ if (IEEE80211_IS_CHAN_5GHZ(chan))
pll |= SM(0x28, AR_RTC_SOWL_PLL_DIV);
else
pll |= SM(0x2c, AR_RTC_SOWL_PLL_DIV);
+
} else
pll |= SM(0x2c, AR_RTC_SOWL_PLL_DIV);
} else if (AR_SREV_SOWL_10_OR_LATER(ah)) {
@@ -1402,7 +1404,8 @@ ar5416InitPLL(struct ath_hal *ah, const
pll |= SM(0x1, AR_RTC_SOWL_PLL_CLKSEL);
else if (IEEE80211_IS_CHAN_QUARTER(chan))
pll |= SM(0x2, AR_RTC_SOWL_PLL_CLKSEL);
- else if (IEEE80211_IS_CHAN_5GHZ(chan))
+
+ if (IEEE80211_IS_CHAN_5GHZ(chan))
pll |= SM(0x50, AR_RTC_SOWL_PLL_DIV);
else
pll |= SM(0x58, AR_RTC_SOWL_PLL_DIV);
@@ -1415,7 +1418,8 @@ ar5416InitPLL(struct ath_hal *ah, const
pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
else if (IEEE80211_IS_CHAN_QUARTER(chan))
pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
- else if (IEEE80211_IS_CHAN_5GHZ(chan))
+
+ if (IEEE80211_IS_CHAN_5GHZ(chan))
pll |= SM(0xa, AR_RTC_PLL_DIV);
else
pll |= SM(0xb, AR_RTC_PLL_DIV);
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