Author: yongari
Date: Thu May 12 17:11:31 2011
New Revision: 221817
URL: http://svn.freebsd.org/changeset/base/221817
Log:
Explicitly clear 1000baseT control register for F1 PHY used in
AR8132 FastEthernet controller. The PHY has no ability to
establish a gigabit link. Previously only link parters which
support down-shifting was able to establish link.
This change should fix a long standing link establishment issue of
AR8132.
PR: kern/156935
MFC after: 1 week
Modified:
head/sys/dev/mii/atphy.c
Modified: head/sys/dev/mii/atphy.c
==============================================================================
--- head/sys/dev/mii/atphy.c Thu May 12 17:02:56 2011 (r221816)
+++ head/sys/dev/mii/atphy.c Thu May 12 17:11:31 2011 (r221817)
@@ -359,6 +359,18 @@ atphy_setmedia(struct mii_softc *sc, int
(EXTSR_1000TFDX | EXTSR_1000THDX)) != 0)
PHY_WRITE(sc, MII_100T2CR, GTCR_ADV_1000TFDX |
GTCR_ADV_1000THDX);
+ else if (sc->mii_mpd_model == MII_MODEL_xxATHEROS_F1) {
+ /*
+ * AR8132 has 10/100 PHY and the PHY uses the same
+ * model number of F1 gigabit PHY. The PHY has no
+ * ability to establish gigabit link so explicitly
+ * disable 1000baseT configuration for the PHY.
+ * Otherwise, there is a case that atphy(4) could
+ * not establish a link against gigabit link partner
+ * unless the link partner supports down-shifting.
+ */
+ PHY_WRITE(sc, MII_100T2CR, 0);
+ }
PHY_WRITE(sc, MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG);
return (EJUSTRETURN);
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