Author: jkim
Date: Fri May 20 22:38:02 2011
New Revision: 222153
URL: http://svn.freebsd.org/changeset/base/222153
Log:
MFC: r222043
Update CPUID bits to reflect AMD Bulldozer and Intel Sandy Bridge features.
Modified:
stable/8/sys/amd64/amd64/identcpu.c
stable/8/sys/amd64/include/specialreg.h
stable/8/sys/i386/i386/identcpu.c
stable/8/sys/i386/include/specialreg.h
Directory Properties:
stable/8/sys/ (props changed)
stable/8/sys/amd64/include/xen/ (props changed)
stable/8/sys/cddl/contrib/opensolaris/ (props changed)
stable/8/sys/contrib/dev/acpica/ (props changed)
stable/8/sys/contrib/pf/ (props changed)
Modified: stable/8/sys/amd64/amd64/identcpu.c
==============================================================================
--- stable/8/sys/amd64/amd64/identcpu.c Fri May 20 22:36:17 2011
(r222152)
+++ stable/8/sys/amd64/amd64/identcpu.c Fri May 20 22:38:02 2011
(r222153)
@@ -212,6 +212,14 @@ printcpuinfo(void)
printf(" Family = %x", CPUID_TO_FAMILY(cpu_id));
printf(" Model = %x", CPUID_TO_MODEL(cpu_id));
printf(" Stepping = %u", cpu_id & CPUID_STEPPING);
+
+ /*
+ * AMD CPUID Specification
+ * http://support.amd.com/us/Embedded_TechDocs/25481.pdf
+ *
+ * Intel Processor Identification and CPUID Instruction
+ * http://www.intel.com/assets/pdf/appnote/241618.pdf
+ */
if (cpu_high > 0) {
/*
@@ -273,38 +281,29 @@ printcpuinfo(void)
"\012SSSE3" /* SSSE3 */
"\013CNXT-ID" /* L1 context ID available */
"\014<b11>"
- "\015<b12>"
+ "\015FMA" /* Fused Multiply Add */
"\016CX16" /* CMPXCHG16B Instruction */
"\017xTPR" /* Send Task Priority Messages*/
"\020PDCM" /* Perf/Debug Capability MSR */
"\021<b16>"
- "\022PCID" /* Process-context Identifiers
*/
+ "\022PCID" /* Process-context Identifiers*/
"\023DCA" /* Direct Cache Access */
- "\024SSE4.1"
- "\025SSE4.2"
+ "\024SSE4.1" /* SSE 4.1 */
+ "\025SSE4.2" /* SSE 4.2 */
"\026x2APIC" /* xAPIC Extensions */
- "\027MOVBE"
- "\030POPCNT"
- "\031<b24>"
- "\032AESNI" /* AES Crypto*/
- "\033XSAVE"
- "\034OSXSAVE"
- "\035<b28>"
- "\036<b29>"
+ "\027MOVBE" /* MOVBE Instruction */
+ "\030POPCNT" /* POPCNT Instruction */
+ "\031TSCDLT" /* TSC-Deadline Timer */
+ "\032AESNI" /* AES Crypto */
+ "\033XSAVE" /* XSAVE/XRSTOR States */
+ "\034OSXSAVE" /* OS-Enabled State Management*/
+ "\035AVX" /* Advanced Vector Extensions */
+ "\036F16C" /* Half-precision conversions */
"\037<b30>"
"\040HV" /* Hypervisor */
);
}
- /*
- * AMD64 Architecture Programmer's Manual Volume 3:
- * General-Purpose and System Instructions
- *
http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/24594.pdf
- *
- * IA-32 Intel Architecture Software Developer's Manual,
- * Volume 2A: Instruction Set Reference, A-M
- *
ftp://download.intel.com/design/Pentium4/manuals/25366617.pdf
- */
if (amd_feature != 0) {
printf("\n AMD Features=0x%b", amd_feature,
"\020" /* in hex */
@@ -357,18 +356,18 @@ printcpuinfo(void)
"\011Prefetch" /* 3DNow! Prefetch/PrefetchW */
"\012OSVW" /* OS visible workaround */
"\013IBS" /* Instruction based sampling */
- "\014SSE5" /* SSE5 */
+ "\014XOP" /* XOP extended instructions */
"\015SKINIT" /* SKINIT/STGI */
"\016WDT" /* Watchdog timer */
"\017<b14>"
- "\020<b15>"
- "\021<b16>"
+ "\020LWP" /* Lightweight Profiling */
+ "\021FMA4" /* 4-operand FMA instructions */
"\022<b17>"
"\023<b18>"
- "\024<b19>"
+ "\024NodeId" /* NodeId MSR support */
"\025<b20>"
- "\026<b21>"
- "\027<b22>"
+ "\026TBM" /* Trailing Bit Manipulation */
+ "\027Topology" /* Topology Extensions */
"\030<b23>"
"\031<b24>"
"\032<b25>"
Modified: stable/8/sys/amd64/include/specialreg.h
==============================================================================
--- stable/8/sys/amd64/include/specialreg.h Fri May 20 22:36:17 2011
(r222152)
+++ stable/8/sys/amd64/include/specialreg.h Fri May 20 22:38:02 2011
(r222153)
@@ -123,6 +123,7 @@
#define CPUID2_TM2 0x00000100
#define CPUID2_SSSE3 0x00000200
#define CPUID2_CNXTID 0x00000400
+#define CPUID2_FMA 0x00001000
#define CPUID2_CX16 0x00002000
#define CPUID2_XTPR 0x00004000
#define CPUID2_PDCM 0x00008000
@@ -133,7 +134,12 @@
#define CPUID2_X2APIC 0x00200000
#define CPUID2_MOVBE 0x00400000
#define CPUID2_POPCNT 0x00800000
+#define CPUID2_TSCDLT 0x01000000
#define CPUID2_AESNI 0x02000000
+#define CPUID2_XSAVE 0x04000000
+#define CPUID2_OSXSAVE 0x08000000
+#define CPUID2_AVX 0x10000000
+#define CPUID2_F16C 0x20000000
#define CPUID2_HV 0x80000000
/*
@@ -170,9 +176,14 @@
#define AMDID2_PREFETCH 0x00000100
#define AMDID2_OSVW 0x00000200
#define AMDID2_IBS 0x00000400
-#define AMDID2_SSE5 0x00000800
+#define AMDID2_XOP 0x00000800
#define AMDID2_SKINIT 0x00001000
#define AMDID2_WDT 0x00002000
+#define AMDID2_LWP 0x00008000
+#define AMDID2_FMA4 0x00010000
+#define AMDID2_NODE_ID 0x00080000
+#define AMDID2_TBM 0x00200000
+#define AMDID2_TOPOLOGY 0x00400000
/*
* CPUID instruction 1 eax info
Modified: stable/8/sys/i386/i386/identcpu.c
==============================================================================
--- stable/8/sys/i386/i386/identcpu.c Fri May 20 22:36:17 2011
(r222152)
+++ stable/8/sys/i386/i386/identcpu.c Fri May 20 22:38:02 2011
(r222153)
@@ -676,6 +676,13 @@ printcpuinfo(void)
printf(" Stepping = %u", cpu_id & CPUID_STEPPING);
if (cpu_vendor_id == CPU_VENDOR_CYRIX)
printf("\n DIR=0x%04x", cyrix_did);
+ /*
+ * AMD CPUID Specification
+ * http://support.amd.com/us/Embedded_TechDocs/25481.pdf
+ *
+ * Intel Processor Identification and CPUID Instruction
+ * http://www.intel.com/assets/pdf/appnote/241618.pdf
+ */
if (cpu_high > 0) {
/*
@@ -737,38 +744,29 @@ printcpuinfo(void)
"\012SSSE3" /* SSSE3 */
"\013CNXT-ID" /* L1 context ID available */
"\014<b11>"
- "\015<b12>"
+ "\015FMA" /* Fused Multiply Add */
"\016CX16" /* CMPXCHG16B Instruction */
"\017xTPR" /* Send Task Priority Messages*/
"\020PDCM" /* Perf/Debug Capability MSR */
"\021<b16>"
- "\022PCID" /* Process-context Identifiers
*/
+ "\022PCID" /* Process-context Identifiers*/
"\023DCA" /* Direct Cache Access */
- "\024SSE4.1"
- "\025SSE4.2"
+ "\024SSE4.1" /* SSE 4.1 */
+ "\025SSE4.2" /* SSE 4.2 */
"\026x2APIC" /* xAPIC Extensions */
- "\027MOVBE"
- "\030POPCNT"
- "\031<b24>"
- "\032AESNI" /* AES Crypto*/
- "\033XSAVE"
- "\034OSXSAVE"
- "\035<b28>"
- "\036<b29>"
+ "\027MOVBE" /* MOVBE Instruction */
+ "\030POPCNT" /* POPCNT Instruction */
+ "\031TSCDLT" /* TSC-Deadline Timer */
+ "\032AESNI" /* AES Crypto */
+ "\033XSAVE" /* XSAVE/XRSTOR States */
+ "\034OSXSAVE" /* OS-Enabled State Management*/
+ "\035AVX" /* Advanced Vector Extensions */
+ "\036F16C" /* Half-precision conversions */
"\037<b30>"
"\040HV" /* Hypervisor */
);
}
- /*
- * AMD64 Architecture Programmer's Manual Volume 3:
- * General-Purpose and System Instructions
- *
http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/24594.pdf
- *
- * IA-32 Intel Architecture Software Developer's Manual,
- * Volume 2A: Instruction Set Reference, A-M
- *
ftp://download.intel.com/design/Pentium4/manuals/25366617.pdf
- */
if (amd_feature != 0) {
printf("\n AMD Features=0x%b", amd_feature,
"\020" /* in hex */
@@ -821,18 +819,18 @@ printcpuinfo(void)
"\011Prefetch" /* 3DNow! Prefetch/PrefetchW */
"\012OSVW" /* OS visible workaround */
"\013IBS" /* Instruction based sampling */
- "\014SSE5" /* SSE5 */
+ "\014XOP" /* XOP extended instructions */
"\015SKINIT" /* SKINIT/STGI */
"\016WDT" /* Watchdog timer */
"\017<b14>"
- "\020<b15>"
- "\021<b16>"
+ "\020LWP" /* Lightweight Profiling */
+ "\021FMA4" /* 4-operand FMA instructions */
"\022<b17>"
"\023<b18>"
- "\024<b19>"
+ "\024NodeId" /* NodeId MSR support */
"\025<b20>"
- "\026<b21>"
- "\027<b22>"
+ "\026TBM" /* Trailing Bit Manipulation */
+ "\027Topology" /* Topology Extensions */
"\030<b23>"
"\031<b24>"
"\032<b25>"
Modified: stable/8/sys/i386/include/specialreg.h
==============================================================================
--- stable/8/sys/i386/include/specialreg.h Fri May 20 22:36:17 2011
(r222152)
+++ stable/8/sys/i386/include/specialreg.h Fri May 20 22:38:02 2011
(r222153)
@@ -120,6 +120,7 @@
#define CPUID2_TM2 0x00000100
#define CPUID2_SSSE3 0x00000200
#define CPUID2_CNXTID 0x00000400
+#define CPUID2_FMA 0x00001000
#define CPUID2_CX16 0x00002000
#define CPUID2_XTPR 0x00004000
#define CPUID2_PDCM 0x00008000
@@ -130,7 +131,12 @@
#define CPUID2_X2APIC 0x00200000
#define CPUID2_MOVBE 0x00400000
#define CPUID2_POPCNT 0x00800000
+#define CPUID2_TSCDLT 0x01000000
#define CPUID2_AESNI 0x02000000
+#define CPUID2_XSAVE 0x04000000
+#define CPUID2_OSXSAVE 0x08000000
+#define CPUID2_AVX 0x10000000
+#define CPUID2_F16C 0x20000000
#define CPUID2_HV 0x80000000
/*
@@ -167,9 +173,14 @@
#define AMDID2_PREFETCH 0x00000100
#define AMDID2_OSVW 0x00000200
#define AMDID2_IBS 0x00000400
-#define AMDID2_SSE5 0x00000800
+#define AMDID2_XOP 0x00000800
#define AMDID2_SKINIT 0x00001000
#define AMDID2_WDT 0x00002000
+#define AMDID2_LWP 0x00008000
+#define AMDID2_FMA4 0x00010000
+#define AMDID2_NODE_ID 0x00080000
+#define AMDID2_TBM 0x00200000
+#define AMDID2_TOPOLOGY 0x00400000
/*
* CPUID instruction 1 eax info
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