On Mon, 2012-08-20 at 13:55 -0700, Adrian Chadd wrote: > I have a report that AR71XX (MIPS) USB broke with this change. > > Hans, would you mind reverting it until we figure out what's going on > in the non-intel USB world? > > Thanks, > > > Adrian
It appears that the change in structure sizes has resulted in things shuffling around in memory in a way that triggers a partial cacheline flush bug in the busdma routines for ARM (and I guess for MIPS too). I'm chasing the actual bug in the ARM code, since it's now 100% reproducible. I'm hoping it's the concrete proof for a bug I've long thought was possible in theory. In the meantime, a quick and easy way to work around the problem is to add to your kernel config: option USB_HOST_ALIGN=32 # data cache line size on your platform Since it appears (at least until some evidence points elsewhere) that the problem is in the busdma code for architectures with VIVT caches, I'm not sure reverting the usb changes would be the right move. Avoiding an MFC until we know more might be a good idea, though. -- Ian _______________________________________________ svn-src-all@freebsd.org mailing list http://lists.freebsd.org/mailman/listinfo/svn-src-all To unsubscribe, send any mail to "svn-src-all-unsubscr...@freebsd.org"
