Author: jimharris
Date: Tue Dec 18 23:27:18 2012
New Revision: 244413
URL: http://svnweb.freebsd.org/changeset/base/244413
Log:
Map BAR 4/5, because NVMe spec says devices may place the MSI-X table
behind BAR 4/5, rather than in BAR 0/1 with the control/doorbell registers.
Sponsored by: Intel
Modified:
head/sys/dev/nvme/nvme.c
head/sys/dev/nvme/nvme_ctrlr.c
head/sys/dev/nvme/nvme_private.h
Modified: head/sys/dev/nvme/nvme.c
==============================================================================
--- head/sys/dev/nvme/nvme.c Tue Dec 18 22:18:54 2012 (r244412)
+++ head/sys/dev/nvme/nvme.c Tue Dec 18 23:27:18 2012 (r244413)
@@ -313,6 +313,11 @@ nvme_detach (device_t dev)
ctrlr->resource_id, ctrlr->resource);
}
+ if (ctrlr->bar4_resource != NULL) {
+ bus_release_resource(dev, SYS_RES_MEMORY,
+ ctrlr->bar4_resource_id, ctrlr->bar4_resource);
+ }
+
#ifdef CHATHAM2
if (ctrlr->chatham_resource != NULL) {
bus_release_resource(dev, SYS_RES_MEMORY,
Modified: head/sys/dev/nvme/nvme_ctrlr.c
==============================================================================
--- head/sys/dev/nvme/nvme_ctrlr.c Tue Dec 18 22:18:54 2012
(r244412)
+++ head/sys/dev/nvme/nvme_ctrlr.c Tue Dec 18 23:27:18 2012
(r244413)
@@ -78,6 +78,17 @@ nvme_ctrlr_allocate_bar(struct nvme_cont
ctrlr->bus_handle = rman_get_bushandle(ctrlr->resource);
ctrlr->regs = (struct nvme_registers *)ctrlr->bus_handle;
+ /*
+ * The NVMe spec allows for the MSI-X table to be placed behind
+ * BAR 4/5, separate from the control/doorbell registers. Always
+ * try to map this bar, because it must be mapped prior to calling
+ * pci_alloc_msix(). If the table isn't behind BAR 4/5,
+ * bus_alloc_resource() will just return NULL which is OK.
+ */
+ ctrlr->bar4_resource_id = PCIR_BAR(4);
+ ctrlr->bar4_resource = bus_alloc_resource(ctrlr->dev, SYS_RES_MEMORY,
+ &ctrlr->bar4_resource_id, 0, ~0, 1, RF_ACTIVE);
+
return (0);
}
Modified: head/sys/dev/nvme/nvme_private.h
==============================================================================
--- head/sys/dev/nvme/nvme_private.h Tue Dec 18 22:18:54 2012
(r244412)
+++ head/sys/dev/nvme/nvme_private.h Tue Dec 18 23:27:18 2012
(r244413)
@@ -199,6 +199,14 @@ struct nvme_controller {
int resource_id;
struct resource *resource;
+ /*
+ * The NVMe spec allows for the MSI-X table to be placed in BAR 4/5,
+ * separate from the control registers which are in BAR 0/1. These
+ * members track the mapping of BAR 4/5 for that reason.
+ */
+ int bar4_resource_id;
+ struct resource *bar4_resource;
+
#ifdef CHATHAM2
bus_space_tag_t chatham_bus_tag;
bus_space_handle_t chatham_bus_handle;
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