On Mon, 8 Apr 2013, Gleb Smirnoff wrote:
On Mon, Apr 08, 2013 at 03:41:27PM -0400, John Baldwin wrote:
J> On Monday, April 08, 2013 3:19:10 pm Gleb Smirnoff wrote:
J> > Author: glebius
J> > Date: Mon Apr 8 19:19:10 2013
J> > New Revision: 249265
J> > URL: http://svnweb.freebsd.org/changeset/base/249265
J> >
J> > Log:
J> > Merge from projects/counters:
J> >
J> > Pad struct pcpu so that its size is denominator of PAGE_SIZE. This
J> > is done to reduce memory waste in UMA_PCPU_ZONE zones.
J> >
J> > Sponsored by: Nginx, Inc.
J> >
J> > Modified: head/sys/sys/pcpu.h
J> >
J>
==============================================================================
J> > --- head/sys/sys/pcpu.h Mon Apr 8 19:10:45 2013 (r249264)
J> > +++ head/sys/sys/pcpu.h Mon Apr 8 19:19:10 2013 (r249265)
J> > @@ -180,6 +180,14 @@ struct pcpu {
J> > PCPU_MD_FIELDS;
J> > } __aligned(CACHE_LINE_SIZE);
J>
J> Why not change this to be PAGE_SIZE rather than putting explicit padding in
J> all the pcpu fields? That would seem to be more maintainable.
Because it can be smaller than PAGE_SIZE. Two times smaller, four times smaller.
I said in private mail that I don't see a better way to do this.
Now I see a way that might work: #define (in the MD pcpu.h) the expected
number of times smaller (hopefully not fractional). This won't change
very often. Then, if large alignments like PAGE_SIZE work, then smaller
ones like PAGE_SIZE / <number of times smaller> will also work.
How does explicit aligning to only CACHE_LINE_SIZE work anyway? I think
you actually need PAGE_SIZE/N, and get this by magic padding combined
with explicit alignment to only CACHE_LINE_SIZE.
Bruce
Bruce
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