Author: nwhitehorn
Date: Fri Oct 25 14:37:15 2013
New Revision: 257115
URL: http://svnweb.freebsd.org/changeset/base/257115
Log:
Remove some #ifdef and duplication in the MSR bit definitions. This adds
some security features to the Book-E kernel as well.
Modified:
head/sys/powerpc/include/psl.h
head/sys/powerpc/powerpc/exec_machdep.c
head/sys/powerpc/powerpc/genassym.c
Modified: head/sys/powerpc/include/psl.h
==============================================================================
--- head/sys/powerpc/include/psl.h Fri Oct 25 13:29:07 2013
(r257114)
+++ head/sys/powerpc/include/psl.h Fri Oct 25 14:37:15 2013
(r257115)
@@ -35,96 +35,44 @@
#ifndef _MACHINE_PSL_H_
#define _MACHINE_PSL_H_
-#if defined(BOOKE_E500)
/*
- * Machine State Register (MSR) - e500 core
- *
- * The PowerPC e500 does not implement the following bits:
- *
- * FP, FE0, FE1 - reserved, always cleared, setting has no effect.
- *
+ * Machine State Register (MSR) - All cores
*/
+#define PSL_VEC 0x02000000UL /* AltiVec/SPE vector unit
available */
+#define PSL_EE 0x00008000UL /* external interrupt enable */
+#define PSL_PR 0x00004000UL /* privilege mode (1 == user) */
+#define PSL_FP 0x00002000UL /* floating point enable */
+#define PSL_ME 0x00001000UL /* machine check enable */
+#define PSL_FE0 0x00000800UL /* floating point interrupt
mode 0 */
+#define PSL_BE 0x00000200UL /* branch trace enable */
+#define PSL_FE1 0x00000100UL /* floating point interrupt
mode 1 */
+#define PSL_PMM 0x00000004UL /* performance monitor mark */
+
+/* Machine State Register - Book-E cores */
#define PSL_UCLE 0x04000000UL /* User mode cache lock enable */
-#define PSL_SPE 0x02000000UL /* SPE enable */
#define PSL_WE 0x00040000UL /* Wait state enable */
#define PSL_CE 0x00020000UL /* Critical interrupt enable */
-#define PSL_EE 0x00008000UL /* External interrupt enable */
-#define PSL_PR 0x00004000UL /* User mode */
-#define PSL_FP 0x00002000UL /* Floating point available */
-#define PSL_ME 0x00001000UL /* Machine check interrupt enable */
-#define PSL_FE0 0x00000800UL /* Floating point exception
mode 0 */
-#define PSL_UBLE 0x00000400UL /* BTB lock enable */
+#define PSL_UBLE 0x00000400UL /* BTB lock enable - e500 only */
+#define PSL_DWE 0x00000400UL /* Debug Wait Enable - 440
only*/
#define PSL_DE 0x00000200UL /* Debug interrupt enable */
-#define PSL_FE1 0x00000100UL /* Floating point exception
mode 1 */
#define PSL_IS 0x00000020UL /* Instruction address space */
#define PSL_DS 0x00000010UL /* Data address space */
-#define PSL_PMM 0x00000004UL /* Performance monitor mark */
-
-#define PSL_FE_DFLT 0x00000000UL /* default == none */
-
-/* Initial kernel MSR, use IS=1 ad DS=1. */
-#define PSL_KERNSET_INIT (PSL_IS | PSL_DS)
-#define PSL_KERNSET (PSL_CE | PSL_ME | PSL_EE)
-#define PSL_USERSET (PSL_KERNSET | PSL_PR)
-
-#elif defined(BOOKE_PPC4XX)
-/*
- * Machine State Register (MSR) - PPC4xx core
- */
-#define PSL_WE (0x80000000 >> 13) /* Wait State Enable */
-#define PSL_CE (0x80000000 >> 14) /* Critical Interrupt Enable */
-#define PSL_EE (0x80000000 >> 16) /* External Interrupt Enable */
-#define PSL_PR (0x80000000 >> 17) /* Problem State */
-#define PSL_FP (0x80000000 >> 18) /* Floating Point Available */
-#define PSL_ME (0x80000000 >> 19) /* Machine Check Enable */
-#define PSL_FE0 (0x80000000 >> 20) /* Floating-point exception
mode 0 */
-#define PSL_DWE (0x80000000 >> 21) /* Debug Wait Enable */
-#define PSL_DE (0x80000000 >> 22) /* Debug interrupt Enable */
-#define PSL_FE1 (0x80000000 >> 23) /* Floating-point exception
mode 1 */
-#define PSL_IS (0x80000000 >> 26) /* Instruction Address Space */
-#define PSL_DS (0x80000000 >> 27) /* Data Address Space */
-
-#define PSL_KERNSET (PSL_CE | PSL_ME | PSL_EE | PSL_FP)
-#define PSL_USERSET (PSL_KERNSET | PSL_PR)
-
-#define PSL_FE_DFLT 0x00000000UL /* default == none */
-
-#else /* if defined(BOOKE_*) */
-/*
- * Machine State Register (MSR)
- *
- * The PowerPC 601 does not implement the following bits:
- *
- * VEC, POW, ILE, BE, RI, LE[*]
- *
- * [*] Little-endian mode on the 601 is implemented in the HID0 register.
- */
+/* Machine State Register (MSR) - AIM cores */
#ifdef __powerpc64__
#define PSL_SF 0x8000000000000000UL /* 64-bit addressing */
#define PSL_HV 0x1000000000000000UL /* hyper-privileged mode */
#endif
-#define PSL_VEC 0x02000000UL /* AltiVec vector unit
available */
#define PSL_POW 0x00040000UL /* power management */
#define PSL_ILE 0x00010000UL /* interrupt endian mode (1 ==
le) */
-#define PSL_EE 0x00008000UL /* external interrupt enable */
-#define PSL_PR 0x00004000UL /* privilege mode (1 == user) */
-#define PSL_FP 0x00002000UL /* floating point enable */
-#define PSL_ME 0x00001000UL /* machine check enable */
-#define PSL_FE0 0x00000800UL /* floating point interrupt
mode 0 */
#define PSL_SE 0x00000400UL /* single-step trace enable */
-#define PSL_BE 0x00000200UL /* branch trace enable */
-#define PSL_FE1 0x00000100UL /* floating point interrupt
mode 1 */
-#define PSL_IP 0x00000040UL /* interrupt prefix */
+#define PSL_IP 0x00000040UL /* interrupt prefix - 601 only
*/
#define PSL_IR 0x00000020UL /* instruction address
relocation */
#define PSL_DR 0x00000010UL /* data address relocation */
-#define PSL_PMM 0x00000004UL /* performance monitor mark */
#define PSL_RI 0x00000002UL /* recoverable interrupt */
#define PSL_LE 0x00000001UL /* endian mode (1 == le) */
-#define PSL_601_MASK ~(PSL_POW|PSL_ILE|PSL_BE|PSL_RI|PSL_LE)
-
/*
* Floating-point exception modes:
*/
@@ -134,20 +82,21 @@
#define PSL_FE_PREC (PSL_FE0 | PSL_FE1) /* precise */
#define PSL_FE_DFLT PSL_FE_DIS /* default == none */
-/*
- * Note that PSL_POW and PSL_ILE are not in the saved copy of the MSR
- */
-#define PSL_MBO 0
-#define PSL_MBZ 0
-
+#if defined(BOOKE_E500)
+/* Initial kernel MSR, use IS=1 ad DS=1. */
+#define PSL_KERNSET_INIT (PSL_IS | PSL_DS)
+#define PSL_KERNSET (PSL_CE | PSL_ME | PSL_EE)
+#elif defined(BOOKE_PPC4XX)
+#define PSL_KERNSET (PSL_CE | PSL_ME | PSL_EE | PSL_FP)
+#elif defined(AIM)
#ifdef __powerpc64__
#define PSL_KERNSET (PSL_SF | PSL_EE | PSL_ME | PSL_IR | PSL_DR |
PSL_RI)
#else
#define PSL_KERNSET (PSL_EE | PSL_ME | PSL_IR | PSL_DR | PSL_RI)
#endif
-#define PSL_USERSET (PSL_KERNSET | PSL_PR)
+#endif
-#define PSL_USERSTATIC (PSL_USERSET | PSL_IP | 0x87c0008c)
+#define PSL_USERSET (PSL_KERNSET | PSL_PR)
+#define PSL_USERSTATIC ~(PSL_VEC | PSL_FP | PSL_FE0 | PSL_FE1)
-#endif /* if defined(BOOKE_E500) */
#endif /* _MACHINE_PSL_H_ */
Modified: head/sys/powerpc/powerpc/exec_machdep.c
==============================================================================
--- head/sys/powerpc/powerpc/exec_machdep.c Fri Oct 25 13:29:07 2013
(r257114)
+++ head/sys/powerpc/powerpc/exec_machdep.c Fri Oct 25 14:37:15 2013
(r257115)
@@ -449,14 +449,12 @@ set_mcontext(struct thread *td, const mc
if (mcp->mc_vers != _MC_VERSION || mcp->mc_len != sizeof(*mcp))
return (EINVAL);
-#ifdef AIM
/*
* Don't let the user set privileged MSR bits
*/
if ((mcp->mc_srr1 & PSL_USERSTATIC) != (tf->srr1 & PSL_USERSTATIC)) {
return (EINVAL);
}
-#endif
/* Copy trapframe, preserving TLS pointer across context change */
if (SV_PROC_FLAG(td->td_proc, SV_LP64))
@@ -594,7 +592,7 @@ ppc32_setregs(struct thread *td, struct
tf->fixreg[8] = (register_t)imgp->ps_strings; /* NetBSD extension */
tf->srr0 = imgp->entry_addr;
- tf->srr1 = PSL_MBO | PSL_USERSET | PSL_FE_DFLT;
+ tf->srr1 = PSL_USERSET | PSL_FE_DFLT;
tf->srr1 &= ~PSL_SF;
if (mfmsr() & PSL_HV)
tf->srr1 |= PSL_HV;
@@ -1024,7 +1022,7 @@ cpu_set_upcall_kse(struct thread *td, vo
if (SV_PROC_FLAG(td->td_proc, SV_ILP32)) {
tf->srr0 = (register_t)entry;
#ifdef AIM
- tf->srr1 = PSL_MBO | PSL_USERSET | PSL_FE_DFLT;
+ tf->srr1 = PSL_USERSET | PSL_FE_DFLT;
#ifdef __powerpc64__
tf->srr1 &= ~PSL_SF;
#endif
Modified: head/sys/powerpc/powerpc/genassym.c
==============================================================================
--- head/sys/powerpc/powerpc/genassym.c Fri Oct 25 13:29:07 2013
(r257114)
+++ head/sys/powerpc/powerpc/genassym.c Fri Oct 25 14:37:15 2013
(r257115)
@@ -214,28 +214,25 @@ ASSYM(SF_UC, offsetof(struct sigframe, s
ASSYM(KERNBASE, KERNBASE);
ASSYM(MAXCOMLEN, MAXCOMLEN);
-#if defined(BOOKE)
ASSYM(PSL_DE, PSL_DE);
ASSYM(PSL_DS, PSL_DS);
ASSYM(PSL_IS, PSL_IS);
ASSYM(PSL_CE, PSL_CE);
-#endif
-#if defined(BOOKE_E500)
ASSYM(PSL_UCLE, PSL_UCLE);
-ASSYM(PSL_SPE, PSL_SPE);
ASSYM(PSL_WE, PSL_WE);
ASSYM(PSL_UBLE, PSL_UBLE);
+#if defined(BOOKE_E500)
ASSYM(PSL_KERNSET_INIT, PSL_KERNSET_INIT);
-#elif defined(AIM)
-#ifdef __powerpc64__
+#endif
+
+#if defined(AIM) && defined(__powerpc64__)
ASSYM(PSL_SF, PSL_SF);
ASSYM(PSL_HV, PSL_HV);
#endif
-ASSYM(PSL_VEC, PSL_VEC);
+
ASSYM(PSL_POW, PSL_POW);
ASSYM(PSL_ILE, PSL_ILE);
-ASSYM(PSL_BE, PSL_BE);
ASSYM(PSL_LE, PSL_LE);
ASSYM(PSL_SE, PSL_SE);
ASSYM(PSL_RI, PSL_RI);
@@ -248,18 +245,16 @@ ASSYM(PSL_FE_NONREC, PSL_FE_NONREC);
ASSYM(PSL_FE_PREC, PSL_FE_PREC);
ASSYM(PSL_FE_REC, PSL_FE_REC);
-ASSYM(PSL_USERSTATIC, PSL_USERSTATIC);
-#endif
-
+ASSYM(PSL_VEC, PSL_VEC);
+ASSYM(PSL_BE, PSL_BE);
ASSYM(PSL_EE, PSL_EE);
ASSYM(PSL_FE0, PSL_FE0);
ASSYM(PSL_FE1, PSL_FE1);
ASSYM(PSL_FP, PSL_FP);
ASSYM(PSL_ME, PSL_ME);
ASSYM(PSL_PR, PSL_PR);
-#if defined(BOOKE_E500)
ASSYM(PSL_PMM, PSL_PMM);
-#endif
ASSYM(PSL_KERNSET, PSL_KERNSET);
ASSYM(PSL_USERSET, PSL_USERSET);
+ASSYM(PSL_USERSTATIC, PSL_USERSTATIC);
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