Author: yongari
Date: Fri Apr 30 00:34:00 2010
New Revision: 207409
URL: http://svn.freebsd.org/changeset/base/207409
Log:
Both RX_GMF_LP_THR and RX_GMF_UP_THR must be 16 bits register. If
it is 8bits register then RX FIFO size can't exceed 2KB which is
not true for almost all Yukon II controller.
Modified:
head/sys/dev/msk/if_msk.c
head/sys/dev/msk/if_mskreg.h
Modified: head/sys/dev/msk/if_msk.c
==============================================================================
--- head/sys/dev/msk/if_msk.c Fri Apr 30 00:30:29 2010 (r207408)
+++ head/sys/dev/msk/if_msk.c Fri Apr 30 00:34:00 2010 (r207409)
@@ -3822,9 +3822,9 @@ msk_init_locked(struct msk_if_softc *sc_
if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) == 0) {
/* Set Rx Pause threshould. */
- CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, RX_GMF_LP_THR),
+ CSR_WRITE_2(sc, MR_ADDR(sc_if->msk_port, RX_GMF_LP_THR),
MSK_ECU_LLPP);
- CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, RX_GMF_UP_THR),
+ CSR_WRITE_2(sc, MR_ADDR(sc_if->msk_port, RX_GMF_UP_THR),
MSK_ECU_ULPP);
/* Configure store-and-forward for Tx. */
msk_set_tx_stfwd(sc_if);
Modified: head/sys/dev/msk/if_mskreg.h
==============================================================================
--- head/sys/dev/msk/if_mskreg.h Fri Apr 30 00:30:29 2010
(r207408)
+++ head/sys/dev/msk/if_mskreg.h Fri Apr 30 00:34:00 2010
(r207409)
@@ -621,8 +621,8 @@
#define RX_GMF_FL_MSK 0x0c4c /* 32 bit Rx GMAC FIFO Flush Mask */
#define RX_GMF_FL_THR 0x0c50 /* 32 bit Rx GMAC FIFO Flush Threshold */
#define RX_GMF_TR_THR 0x0c54 /* 32 bit Rx Truncation Threshold (Yukon-2) */
-#define RX_GMF_UP_THR 0x0c58 /* 8 bit Rx Upper Pause Thr
(Yukon-EC_U) */
-#define RX_GMF_LP_THR 0x0c5a /* 8 bit Rx Lower Pause Thr
(Yukon-EC_U) */
+#define RX_GMF_UP_THR 0x0c58 /* 16 bit Rx Upper Pause Thr
(Yukon-EC_U) */
+#define RX_GMF_LP_THR 0x0c5a /* 16 bit Rx Lower Pause Thr
(Yukon-EC_U) */
#define RX_GMF_VLAN 0x0c5c /* 32 bit Rx VLAN Type Register (Yukon-2) */
#define RX_GMF_WP 0x0c60 /* 32 bit Rx GMAC FIFO Write Pointer */
#define RX_GMF_WLEV 0x0c68 /* 32 bit Rx GMAC FIFO Write Level */
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