Author: jchandra
Date: Mon Sep 27 14:50:51 2010
New Revision: 213199
URL: http://svn.freebsd.org/changeset/base/213199
Log:
XLS B0 revision PCI support and related changes.
- XLS B0 and later revision chips have PCIe link 2 & 3 mapped to different
PIC interrupts. Update pic.h, board.h and xlr_pci.c to reflect this.
- remove debug prints in xlr_pci.c
- add more processor IDs to board.h, add function xlr_is_xls_b0()
- some style(9) and whitespace fixes
Modified:
head/sys/mips/rmi/board.h
head/sys/mips/rmi/pic.h
head/sys/mips/rmi/xlr_pci.c
Modified: head/sys/mips/rmi/board.h
==============================================================================
--- head/sys/mips/rmi/board.h Mon Sep 27 09:42:31 2010 (r213198)
+++ head/sys/mips/rmi/board.h Mon Sep 27 14:50:51 2010 (r213199)
@@ -30,22 +30,22 @@
* $FreeBSD$
*/
#ifndef _RMI_BOARD_H_
-#define _RMI_BOARD_H_
+#define _RMI_BOARD_H_
/*
* Engineering boards have a major/minor number in their EEPROM to
* identify their configuration
*/
-#define RMI_XLR_BOARD_ARIZONA_I 1
-#define RMI_XLR_BOARD_ARIZONA_II 2
-#define RMI_XLR_BOARD_ARIZONA_III 3
-#define RMI_XLR_BOARD_ARIZONA_IV 4
-#define RMI_XLR_BOARD_ARIZONA_V 5
-#define RMI_XLR_BOARD_ARIZONA_VI 6
-#define RMI_XLR_BOARD_ARIZONA_VII 7
-#define RMI_XLR_BOARD_ARIZONA_VIII 8
-#define RMI_XLR_BOARD_ARIZONA_XI 11
-#define RMI_XLR_BOARD_ARIZONA_XII 12
+#define RMI_XLR_BOARD_ARIZONA_I 1
+#define RMI_XLR_BOARD_ARIZONA_II 2
+#define RMI_XLR_BOARD_ARIZONA_III 3
+#define RMI_XLR_BOARD_ARIZONA_IV 4
+#define RMI_XLR_BOARD_ARIZONA_V 5
+#define RMI_XLR_BOARD_ARIZONA_VI 6
+#define RMI_XLR_BOARD_ARIZONA_VII 7
+#define RMI_XLR_BOARD_ARIZONA_VIII 8
+#define RMI_XLR_BOARD_ARIZONA_XI 11
+#define RMI_XLR_BOARD_ARIZONA_XII 12
/*
* RMI Chips - Values in Processor ID field
@@ -55,24 +55,39 @@
#define RMI_CHIP_XLR308 0x06
#define RMI_CHIP_XLR532 0x09
-#define RMI_CHIP_XLS616_B0 0x40
-#define RMI_CHIP_XLS608_B0 0x4a
-#define RMI_CHIP_XLS608 0x80 /* Internal */
-#define RMI_CHIP_XLS416_B0 0x44
-#define RMI_CHIP_XLS412_B0 0x4c
-#define RMI_CHIP_XLS408_B0 0x4e
-#define RMI_CHIP_XLS408 0x88 /* Lite "Condor" */
-#define RMI_CHIP_XLS404_B0 0x4f
-#define RMI_CHIP_XLS404 0x8c /* Lite "Condor" */
-#define RMI_CHIP_XLS208 0x8e
-#define RMI_CHIP_XLS204 0x8f
-#define RMI_CHIP_XLS108 0xce
-#define RMI_CHIP_XLS104 0xcf
+/*
+ * XLR C revisions
+ */
+#define RMI_CHIP_XLR308_C 0x0F
+#define RMI_CHIP_XLR508_C 0x0b
+#define RMI_CHIP_XLR516_C 0x0a
+#define RMI_CHIP_XLR532_C 0x08
+
+/*
+ * XLS processors
+ */
+#define RMI_CHIP_XLS408 0x88 /* Lite "Condor" */
+#define RMI_CHIP_XLS608 0x80 /* Internal */
+#define RMI_CHIP_XLS404 0x8c /* Lite "Condor" */
+#define RMI_CHIP_XLS208 0x8e
+#define RMI_CHIP_XLS204 0x8f
+#define RMI_CHIP_XLS108 0xce
+#define RMI_CHIP_XLS104 0xcf
+
+/*
+ * XLS B revision chips
+ */
+#define RMI_CHIP_XLS616_B0 0x40
+#define RMI_CHIP_XLS608_B0 0x4a
+#define RMI_CHIP_XLS416_B0 0x44
+#define RMI_CHIP_XLS412_B0 0x4c
+#define RMI_CHIP_XLS408_B0 0x4e
+#define RMI_CHIP_XLS404_B0 0x4f
/*
* The XLS product line has chip versions 0x4x and 0x8x
*/
-static __inline__ unsigned int
+static __inline unsigned int
xlr_is_xls(void)
{
uint32_t prid = mips_rd_prid();
@@ -84,18 +99,20 @@ xlr_is_xls(void)
/*
* The last byte of the processor id field is revision
*/
-static __inline__ unsigned int
+static __inline unsigned int
xlr_revision(void)
{
- return mips_rd_prid() & 0xff;
+
+ return (mips_rd_prid() & 0xff);
}
/*
* The 15:8 byte of the PR Id register is the Processor ID
*/
-static __inline__ unsigned int
+static __inline unsigned int
xlr_processor_id(void)
{
+
return ((mips_rd_prid() & 0xff00) >> 8);
}
@@ -103,14 +120,15 @@ xlr_processor_id(void)
* RMI Engineering boards which are PCI cards
* These should come up in PCI device mode (not yet)
*/
-static __inline__ int
+static __inline int
xlr_board_pci(int board_major)
{
+
return ((board_major == RMI_XLR_BOARD_ARIZONA_III) ||
(board_major == RMI_XLR_BOARD_ARIZONA_V));
}
-static __inline__ int
+static __inline int
xlr_is_xls1xx(void)
{
uint32_t chipid = xlr_processor_id();
@@ -118,7 +136,7 @@ xlr_is_xls1xx(void)
return (chipid == 0xce || chipid == 0xcf);
}
-static __inline__ int
+static __inline int
xlr_is_xls2xx(void)
{
uint32_t chipid = xlr_processor_id();
@@ -126,16 +144,24 @@ xlr_is_xls2xx(void)
return (chipid == 0x8e || chipid == 0x8f);
}
-static __inline__ int
+static __inline int
xlr_is_xls4xx_lite(void)
{
uint32_t chipid = xlr_processor_id();
return (chipid == 0x88 || chipid == 0x8c);
- }
-
+}
+
+static __inline unsigned int
+xlr_is_xls_b0(void)
+{
+ uint32_t chipid = xlr_processor_id();
+
+ return (chipid >= 0x40 && chipid <= 0x4f);
+}
+
/* SPI-4 --> 8 ports, 1G MAC --> 4 ports and 10G MAC --> 1 port */
-#define MAX_NA_PORTS 8
+#define MAX_NA_PORTS 8
/* all our knowledge of chip and board that cannot be detected run-time goes
here */
enum gmac_block_types { XLR_GMAC, XLR_XGMAC, XLR_SPI4};
Modified: head/sys/mips/rmi/pic.h
==============================================================================
--- head/sys/mips/rmi/pic.h Mon Sep 27 09:42:31 2010 (r213198)
+++ head/sys/mips/rmi/pic.h Mon Sep 27 14:50:51 2010 (r213199)
@@ -66,6 +66,8 @@
#define PIC_IRT_PCIE_LINK1_INDEX 27
#define PIC_IRT_PCIE_LINK2_INDEX 23
#define PIC_IRT_PCIE_LINK3_INDEX 24
+#define PIC_IRT_PCIE_B0_LINK2_INDEX 28
+#define PIC_IRT_PCIE_B0_LINK3_INDEX 29
#define PIC_IRT_PCIE_INT_INDEX 28
#define PIC_IRT_PCIE_FATAL_INDEX 29
#define PIC_IRT_GPIO_B_INDEX 30
@@ -140,7 +142,9 @@
#define PIC_PCIE_LINK1_IRQ (PIC_IRQ_BASE +
PIC_IRT_PCIE_LINK1_INDEX)
#define PIC_PCIE_LINK2_IRQ (PIC_IRQ_BASE +
PIC_IRT_PCIE_LINK2_INDEX)
#define PIC_PCIE_LINK3_IRQ (PIC_IRQ_BASE +
PIC_IRT_PCIE_LINK3_INDEX)
-#define PIC_PCIE_INT_IRQ (PIC_IRQ_BASE + PIC_IRT_PCIE_INT__INDEX)
+#define PIC_PCIE_B0_LINK2_IRQ (PIC_IRQ_BASE +
PIC_IRT_PCIE_B0_LINK2_INDEX)
+#define PIC_PCIE_B0_LINK3_IRQ (PIC_IRQ_BASE +
PIC_IRT_PCIE_B0_LINK3_INDEX)
+#define PIC_PCIE_INT_IRQ (PIC_IRQ_BASE + PIC_IRT_PCIE_INT_INDEX)
#define PIC_PCIE_FATAL_IRQ (PIC_IRQ_BASE +
PIC_IRT_PCIE_FATAL_INDEX)
#define PIC_GPIO_B_IRQ (PIC_IRQ_BASE + PIC_IRT_GPIO_B_INDEX)
#define PIC_USB_IRQ (PIC_IRQ_BASE + PIC_IRT_USB_INDEX)
Modified: head/sys/mips/rmi/xlr_pci.c
==============================================================================
--- head/sys/mips/rmi/xlr_pci.c Mon Sep 27 09:42:31 2010 (r213198)
+++ head/sys/mips/rmi/xlr_pci.c Mon Sep 27 14:50:51 2010 (r213199)
@@ -310,19 +310,6 @@ static void
xlr_pcib_identify(driver_t * driver, device_t parent)
{
- if (xlr_board_info.is_xls) {
- xlr_reg_t *pcie_mmio_le = xlr_io_mmio(XLR_IO_PCIE_1_OFFSET);
- xlr_reg_t reg_link0 = xlr_read_reg(pcie_mmio_le, (0x80 >> 2));
- xlr_reg_t reg_link1 = xlr_read_reg(pcie_mmio_le, (0x84 >> 2));
-
- if ((uint16_t) reg_link0 & PCIE_LINK_STATE) {
- device_printf(parent, "Link 0 up\n");
- }
- if ((uint16_t) reg_link1 & PCIE_LINK_STATE) {
- device_printf(parent, "Link 1 up\n");
- }
- }
-
BUS_ADD_CHILD(parent, 0, "pcib", 0);
}
@@ -366,9 +353,15 @@ xls_pcie_link_irq(int link)
case 1:
return (PIC_PCIE_LINK1_IRQ);
case 2:
- return (PIC_PCIE_LINK2_IRQ);
+ if (xlr_is_xls_b0())
+ return (PIC_PCIE_B0_LINK2_IRQ);
+ else
+ return (PIC_PCIE_LINK2_IRQ);
case 3:
- return (PIC_PCIE_LINK3_IRQ);
+ if (xlr_is_xls_b0())
+ return (PIC_PCIE_B0_LINK3_IRQ);
+ else
+ return (PIC_PCIE_LINK3_IRQ);
}
return (-1);
}
@@ -395,8 +388,6 @@ xlr_alloc_msi(device_t pcib, device_t de
for (i = 0; i < count; i++)
irqs[i] = 64 + link * 32 + i;
- device_printf(dev, "Alloc MSI count %d maxcount %d irq %d link %d\n",
- count, maxcount, i, link);
return (0);
}
@@ -414,7 +405,6 @@ xlr_map_msi(device_t pcib, device_t dev,
{
int msi;
- device_printf(dev, "MAP MSI irq %d\n", irq);
if (irq >= 64) {
msi = irq - 64;
*addr = MIPS_MSI_ADDR(0);
@@ -448,9 +438,11 @@ bridge_pcie_ack(int irq)
reg = PCIE_LINK1_MSI_STATUS;
break;
case PIC_PCIE_LINK2_IRQ:
+ case PIC_PCIE_B0_LINK2_IRQ:
reg = PCIE_LINK2_MSI_STATUS;
break;
case PIC_PCIE_LINK3_IRQ:
+ case PIC_PCIE_B0_LINK3_IRQ:
reg = PCIE_LINK3_MSI_STATUS;
break;
default:
@@ -476,8 +468,6 @@ mips_platform_pci_setup_intr(device_t de
return (EINVAL);
}
xlrirq = rman_get_start(irq);
- device_printf(dev, "%s: setup intr %d\n", device_get_nameunit(child),
- xlrirq);
if (strcmp(device_get_name(dev), "pcib") != 0)
return (0);
@@ -528,9 +518,6 @@ xlr_pci_alloc_resource(device_t bus, dev
vm_offset_t va;
int needactivate = flags & RF_ACTIVE;
- device_printf(child, "Alloc res type %d, rid %d, start %lx, end %lx,
count %lx flags %u\n",
- type, *rid, start, end, count, flags);
-
switch (type) {
case SYS_RES_IRQ:
rm = &irq_rman;
@@ -603,8 +590,6 @@ mips_pci_route_interrupt(device_t bus, d
/*
* Validate requested pin number.
*/
- device_printf(dev, "route intr pin %d (bus %d, slot %d)\n",
- pin, pci_get_bus(dev), pci_get_slot(dev));
if ((pin < 1) || (pin > 4))
return (255);
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