Author: jmallett
Date: Tue Jan 4 02:11:03 2011
New Revision: 216946
URL: http://svn.freebsd.org/changeset/base/216946
Log:
o) Unmask Central Interrupt Unit interrupts on APs, too.
o) There's no good reason to make the low bits of the ebase the core
number. While per-CPU exception bases would be nice, for now we just
need to make ebase the same on all cores.
Modified:
head/sys/mips/cavium/octeon_mp.c
Modified: head/sys/mips/cavium/octeon_mp.c
==============================================================================
--- head/sys/mips/cavium/octeon_mp.c Tue Jan 4 00:39:56 2011
(r216945)
+++ head/sys/mips/cavium/octeon_mp.c Tue Jan 4 02:11:03 2011
(r216946)
@@ -74,12 +74,12 @@ platform_ipi_intrnum(void)
void
platform_init_ap(int cpuid)
{
- unsigned ipi_int_mask, clock_int_mask;
+ unsigned ciu_int_mask, clock_int_mask, ipi_int_mask;
/*
* Set the exception base.
*/
- mips_wr_ebase(0x80000000 | cpuid);
+ mips_wr_ebase(0x80000000);
/*
* Clear any pending IPIs.
@@ -92,11 +92,12 @@ platform_init_ap(int cpuid)
octeon_ciu_reset();
/*
- * Unmask the clock and ipi interrupts.
+ * Unmask the clock, ipi and ciu interrupts.
*/
+ ciu_int_mask = hard_int_mask(0);
clock_int_mask = hard_int_mask(5);
ipi_int_mask = hard_int_mask(platform_ipi_intrnum());
- set_intr_mask(ipi_int_mask | clock_int_mask);
+ set_intr_mask(ciu_int_mask | clock_int_mask | ipi_int_mask);
mips_wbflush();
}
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