Author: andrew
Date: Sat Jul 28 12:52:03 2018
New Revision: 336830
URL: https://svnweb.freebsd.org/changeset/base/336830
Log:
Remove an unused function from the arm ELF trampoline. It tries to find
properties about the CPU caches, however we never use these values.
Modified:
head/sys/arm/arm/elf_trampoline.c
Modified: head/sys/arm/arm/elf_trampoline.c
==============================================================================
--- head/sys/arm/arm/elf_trampoline.c Sat Jul 28 12:50:09 2018
(r336829)
+++ head/sys/arm/arm/elf_trampoline.c Sat Jul 28 12:52:03 2018
(r336830)
@@ -72,35 +72,6 @@ extern void sheeva_l2cache_wbinv_all(void);
#define cpu_l2cache_wbinv_all()
#endif
-
-int arm_picache_size;
-int arm_picache_line_size;
-int arm_picache_ways;
-
-int arm_pdcache_size; /* and unified */
-int arm_pdcache_line_size = 32;
-int arm_pdcache_ways;
-
-int arm_pcache_type;
-int arm_pcache_unified;
-
-int arm_dcache_align;
-int arm_dcache_align_mask;
-
-int arm_dcache_min_line_size = 32;
-int arm_icache_min_line_size = 32;
-int arm_idcache_min_line_size = 32;
-
-u_int arm_cache_level;
-u_int arm_cache_type[14];
-u_int arm_cache_loc;
-
-/* Additional cache information local to this file. Log2 of some of the
- above numbers. */
-static int arm_dcache_l2_nsets;
-static int arm_dcache_l2_assoc;
-static int arm_dcache_l2_linesize;
-
/*
* Boot parameters
*/
@@ -229,114 +200,6 @@ _startC(unsigned r0, unsigned r1, unsigned r2, unsigne
"mov sp, %2\n"
: "=r" (tmp1), "+r" (kernphysaddr), "+r" (sp));
__start();
-}
-
-static void
-get_cachetype_cp15()
-{
- u_int ctype, isize, dsize, cpuid;
- u_int clevel, csize, i, sel;
- u_int multiplier;
- u_char type;
-
- __asm __volatile("mrc p15, 0, %0, c0, c0, 1"
- : "=r" (ctype));
-
- cpuid = cpu_ident();
- /*
- * ...and thus spake the ARM ARM:
- *
- * If an <opcode2> value corresponding to an unimplemented or
- * reserved ID register is encountered, the System Control
- * processor returns the value of the main ID register.
- */
- if (ctype == cpuid)
- goto out;
-
- if (CPU_CT_FORMAT(ctype) == CPU_CT_ARMV7) {
- /* Resolve minimal cache line sizes */
- arm_dcache_min_line_size = 1 << (CPU_CT_DMINLINE(ctype) + 2);
- arm_icache_min_line_size = 1 << (CPU_CT_IMINLINE(ctype) + 2);
- arm_idcache_min_line_size =
- (arm_dcache_min_line_size > arm_icache_min_line_size ?
- arm_icache_min_line_size : arm_dcache_min_line_size);
-
- __asm __volatile("mrc p15, 1, %0, c0, c0, 1"
- : "=r" (clevel));
- arm_cache_level = clevel;
- arm_cache_loc = CPU_CLIDR_LOC(arm_cache_level) + 1;
- i = 0;
- while ((type = (clevel & 0x7)) && i < 7) {
- if (type == CACHE_DCACHE || type == CACHE_UNI_CACHE ||
- type == CACHE_SEP_CACHE) {
- sel = i << 1;
- __asm __volatile("mcr p15, 2, %0, c0, c0, 0"
- : : "r" (sel));
- __asm __volatile("mrc p15, 1, %0, c0, c0, 0"
- : "=r" (csize));
- arm_cache_type[sel] = csize;
- }
- if (type == CACHE_ICACHE || type == CACHE_SEP_CACHE) {
- sel = (i << 1) | 1;
- __asm __volatile("mcr p15, 2, %0, c0, c0, 0"
- : : "r" (sel));
- __asm __volatile("mrc p15, 1, %0, c0, c0, 0"
- : "=r" (csize));
- arm_cache_type[sel] = csize;
- }
- i++;
- clevel >>= 3;
- }
- } else {
- if ((ctype & CPU_CT_S) == 0)
- arm_pcache_unified = 1;
-
- /*
- * If you want to know how this code works, go read the ARM ARM.
- */
-
- arm_pcache_type = CPU_CT_CTYPE(ctype);
-
- if (arm_pcache_unified == 0) {
- isize = CPU_CT_ISIZE(ctype);
- multiplier = (isize & CPU_CT_xSIZE_M) ? 3 : 2;
- arm_picache_line_size = 1U << (CPU_CT_xSIZE_LEN(isize)
+ 3);
- if (CPU_CT_xSIZE_ASSOC(isize) == 0) {
- if (isize & CPU_CT_xSIZE_M)
- arm_picache_line_size = 0; /* not
present */
- else
- arm_picache_ways = 1;
- } else {
- arm_picache_ways = multiplier <<
- (CPU_CT_xSIZE_ASSOC(isize) - 1);
- }
- arm_picache_size = multiplier <<
(CPU_CT_xSIZE_SIZE(isize) + 8);
- }
-
- dsize = CPU_CT_DSIZE(ctype);
- multiplier = (dsize & CPU_CT_xSIZE_M) ? 3 : 2;
- arm_pdcache_line_size = 1U << (CPU_CT_xSIZE_LEN(dsize) + 3);
- if (CPU_CT_xSIZE_ASSOC(dsize) == 0) {
- if (dsize & CPU_CT_xSIZE_M)
- arm_pdcache_line_size = 0; /* not present */
- else
- arm_pdcache_ways = 1;
- } else {
- arm_pdcache_ways = multiplier <<
- (CPU_CT_xSIZE_ASSOC(dsize) - 1);
- }
- arm_pdcache_size = multiplier << (CPU_CT_xSIZE_SIZE(dsize) + 8);
-
- arm_dcache_align = arm_pdcache_line_size;
-
- arm_dcache_l2_assoc = CPU_CT_xSIZE_ASSOC(dsize) + multiplier -
2;
- arm_dcache_l2_linesize = CPU_CT_xSIZE_LEN(dsize) + 3;
- arm_dcache_l2_nsets = 6 + CPU_CT_xSIZE_SIZE(dsize) -
- CPU_CT_xSIZE_ASSOC(dsize) - CPU_CT_xSIZE_LEN(dsize);
-
- out:
- arm_dcache_align_mask = arm_dcache_align - 1;
- }
}
#ifdef KZIP
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