Author: jhibbits
Date: Fri Apr 12 00:44:33 2019
New Revision: 346143
URL: https://svnweb.freebsd.org/changeset/base/346143
Log:
powerpc64: Increase the nap level on power9 idling
The POWER9 documentation specifies that levels 0-3 are the 'lightest' sleep
level, meaning lowest latency and with no state loss. However, state 3 is
not implemented, and is instead reserved for future chips. This now
properly configures the PSSCR, specifying state 2 as the lowest level to
enter, but request level 0 for quickest sleep level. If the OCC determines
that the CPU can enter states 1 or 2 it will trigger the transition to those
states on demand.
MFC after: 1 week
Modified:
head/sys/powerpc/include/spr.h
head/sys/powerpc/powerpc/cpu.c
Modified: head/sys/powerpc/include/spr.h
==============================================================================
--- head/sys/powerpc/include/spr.h Fri Apr 12 00:31:22 2019
(r346142)
+++ head/sys/powerpc/include/spr.h Fri Apr 12 00:44:33 2019
(r346143)
@@ -412,6 +412,19 @@
#define SPR_MD_RAM0 0x339 /* ..8 IMMU RAM entry read reg
0 */
#define SPR_MD_RAM1 0x33a /* ..8 IMMU RAM entry read reg
1 */
#define SPR_PSSCR 0x357 /* Processor Stop Status and
Control Register (ISA 3.0) */
+#define PSSCR_PLS_S 60
+#define PSSCR_PLS_M (0xf << PSSCR_PLS_S)
+#define PSSCR_SD (1 << 22)
+#define PSSCR_ESL (1 << 21)
+#define PSSCR_EC (1 << 20)
+#define PSSCR_PSLL_S 16
+#define PSSCR_PSLL_M (0xf << PSSCR_PSLL_S)
+#define PSSCR_TR_S 8
+#define PSSCR_TR_M (0x3 << PSSCR_TR_S)
+#define PSSCR_MTL_S 4
+#define PSSCR_MTL_M (0xf << PSSCR_MTL_S)
+#define PSSCR_RL_S 0
+#define PSSCR_RL_M (0xf << PSSCR_RL_S)
#define SPR_PMCR 0x374 /* Processor Management Control
Register */
#define SPR_UMMCR2 0x3a0 /* .6. User Monitor Mode
Control Register 2 */
#define SPR_UMMCR0 0x3a8 /* .6. User Monitor Mode
Control Register 0 */
Modified: head/sys/powerpc/powerpc/cpu.c
==============================================================================
--- head/sys/powerpc/powerpc/cpu.c Fri Apr 12 00:31:22 2019
(r346142)
+++ head/sys/powerpc/powerpc/cpu.c Fri Apr 12 00:44:33 2019
(r346143)
@@ -787,7 +787,6 @@ cpu_idle_booke(sbintime_t sbt)
static void
cpu_idle_powerx(sbintime_t sbt)
{
-
/* Sleeping when running on one cpu gives no advantages - avoid it */
if (smp_started == 0)
return;
@@ -816,7 +815,8 @@ cpu_idle_power9(sbintime_t sbt)
/* Suspend external interrupts until stop instruction completes. */
mtmsr(msr & ~PSL_EE);
/* Set the stop state to lowest latency, wake up to next instruction */
- mtspr(SPR_PSSCR, 0);
+ /* Set maximum transition level to 2, for deepest lossless sleep. */
+ mtspr(SPR_PSSCR, (2 << PSSCR_MTL_S) | (0 << PSSCR_RL_S));
/* "stop" instruction (PowerISA 3.0) */
__asm __volatile (".long 0x4c0002e4");
/*
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