Author: emaste
Date: Thu Dec 12 19:23:38 2019
New Revision: 355666
URL: https://svnweb.freebsd.org/changeset/base/355666
Log:
libpmc: sort some amdfam17h entries to make valid json
Modified:
head/lib/libpmc/pmu-events/arch/x86/amdfam17h/core.json
head/lib/libpmc/pmu-events/arch/x86/amdfam17h/memory.json
Modified: head/lib/libpmc/pmu-events/arch/x86/amdfam17h/core.json
==============================================================================
--- head/lib/libpmc/pmu-events/arch/x86/amdfam17h/core.json Thu Dec 12
19:21:16 2019 (r355665)
+++ head/lib/libpmc/pmu-events/arch/x86/amdfam17h/core.json Thu Dec 12
19:23:38 2019 (r355666)
@@ -2,20 +2,20 @@
{
"EventName": "ex_ret_instr",
"EventCode": "0xc0",
+ "SampleAfterValue": "2000003",
"BriefDescription": "Retired Instructions."
- "SampleAfterValue": "2000003",
},
{
"EventName": "ex_ret_cops",
"EventCode": "0xc1",
+ "SampleAfterValue": "2000003",
"BriefDescription": "The number of uOps retired. This includes all processor
activity (instructions, exceptions, interrupts, microcode assists, etc.). The
number of events logged per cycle can vary from 0 to 4."
- "SampleAfterValue": "2000003",
},
{
"EventName": "ex_ret_brn",
"EventCode": "0xc2",
+ "SampleAfterValue": "2000003",
"BriefDescription": "The number of branch instructions retired. This includes
all types of architectural control flow changes, including exceptions and
interrupts."
- "SampleAfterValue": "2000003",
},
{
"EventName": "ex_ret_brn_misp",
Modified: head/lib/libpmc/pmu-events/arch/x86/amdfam17h/memory.json
==============================================================================
--- head/lib/libpmc/pmu-events/arch/x86/amdfam17h/memory.json Thu Dec 12
19:21:16 2019 (r355665)
+++ head/lib/libpmc/pmu-events/arch/x86/amdfam17h/memory.json Thu Dec 12
19:23:38 2019 (r355666)
@@ -220,7 +220,7 @@
{
"EventName": "ls_not_halted_cyc",
"EventCode": "0x76",
- "BriefDescription": "Cycles not in Halt."
"SampleAfterValue": "2000003",
+ "BriefDescription": "Cycles not in Halt."
}
]
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