Author: mjg
Date: Tue Sep 1 21:20:08 2020
New Revision: 365073
URL: https://svnweb.freebsd.org/changeset/base/365073
Log:
powerpc: clean up empty lines in .c and .h files
Modified:
head/sys/powerpc/aim/aim_machdep.c
head/sys/powerpc/aim/mmu_oea.c
head/sys/powerpc/aim/mmu_oea64.c
head/sys/powerpc/aim/mmu_oea64.h
head/sys/powerpc/aim/mmu_radix.c
head/sys/powerpc/aim/moea64_native.c
head/sys/powerpc/aim/mp_cpudep.c
head/sys/powerpc/aim/slb.c
head/sys/powerpc/amigaone/cpld_a1222.c
head/sys/powerpc/amigaone/cpld_x5000.c
head/sys/powerpc/booke/booke_machdep.c
head/sys/powerpc/booke/platform_bare.c
head/sys/powerpc/booke/pmap.c
head/sys/powerpc/booke/pmap_32.c
head/sys/powerpc/booke/pmap_64.c
head/sys/powerpc/booke/spe.c
head/sys/powerpc/cpufreq/dfs.c
head/sys/powerpc/cpufreq/mpc85xx_jog.c
head/sys/powerpc/cpufreq/pcr.c
head/sys/powerpc/cpufreq/pmcr.c
head/sys/powerpc/cpufreq/pmufreq.c
head/sys/powerpc/fpu/fpu_arith.h
head/sys/powerpc/fpu/fpu_emu.c
head/sys/powerpc/fpu/fpu_explode.c
head/sys/powerpc/fpu/fpu_extern.h
head/sys/powerpc/fpu/fpu_implode.c
head/sys/powerpc/fpu/fpu_instr.h
head/sys/powerpc/include/altivec.h
head/sys/powerpc/include/atomic.h
head/sys/powerpc/include/bat.h
head/sys/powerpc/include/cpufunc.h
head/sys/powerpc/include/mmuvar.h
head/sys/powerpc/include/openpicreg.h
head/sys/powerpc/include/openpicvar.h
head/sys/powerpc/include/pcb.h
head/sys/powerpc/include/pio.h
head/sys/powerpc/include/pmap.h
head/sys/powerpc/include/rtas.h
head/sys/powerpc/include/spr.h
head/sys/powerpc/include/trap.h
head/sys/powerpc/mambo/mambo.c
head/sys/powerpc/mikrotik/rb_led.c
head/sys/powerpc/mpc85xx/atpic.c
head/sys/powerpc/mpc85xx/ds1553_bus_fdt.c
head/sys/powerpc/mpc85xx/ds1553_reg.h
head/sys/powerpc/mpc85xx/fsl_diu.c
head/sys/powerpc/mpc85xx/fsl_sata.c
head/sys/powerpc/mpc85xx/fsl_sata.h
head/sys/powerpc/mpc85xx/i2c.c
head/sys/powerpc/mpc85xx/lbc.c
head/sys/powerpc/mpc85xx/mpc85xx.c
head/sys/powerpc/mpc85xx/mpc85xx_gpio.c
head/sys/powerpc/mpc85xx/pci_mpc85xx.c
head/sys/powerpc/mpc85xx/platform_mpc85xx.c
head/sys/powerpc/mpc85xx/qoriq_gpio.c
head/sys/powerpc/ofw/ofw_initrd.c
head/sys/powerpc/ofw/ofw_machdep.c
head/sys/powerpc/ofw/ofw_pcib_pci.c
head/sys/powerpc/ofw/ofw_pcibus.c
head/sys/powerpc/ofw/ofw_pcibus.h
head/sys/powerpc/ofw/ofw_real.c
head/sys/powerpc/ofw/ofw_syscons.c
head/sys/powerpc/ofw/openpic_ofw.c
head/sys/powerpc/ofw/rtas.c
head/sys/powerpc/powermac/ata_dbdma.c
head/sys/powerpc/powermac/ata_dbdma.h
head/sys/powerpc/powermac/ata_macio.c
head/sys/powerpc/powermac/cpcht.c
head/sys/powerpc/powermac/cuda.c
head/sys/powerpc/powermac/dbdma.c
head/sys/powerpc/powermac/dbdmavar.h
head/sys/powerpc/powermac/grackle.c
head/sys/powerpc/powermac/kiic.c
head/sys/powerpc/powermac/macgpio.c
head/sys/powerpc/powermac/macio.c
head/sys/powerpc/powermac/nvbl.c
head/sys/powerpc/powermac/platform_powermac.c
head/sys/powerpc/powermac/pmu.c
head/sys/powerpc/powermac/pmuvar.h
head/sys/powerpc/powermac/powermac_thermal.c
head/sys/powerpc/powermac/powermac_thermal.h
head/sys/powerpc/powermac/pswitch.c
head/sys/powerpc/powermac/smu.c
head/sys/powerpc/powermac/smusat.c
head/sys/powerpc/powermac/uninorth.c
head/sys/powerpc/powermac/uninorthpci.c
head/sys/powerpc/powermac/uninorthvar.h
head/sys/powerpc/powermac/vcoregpio.c
head/sys/powerpc/powernv/opal.c
head/sys/powerpc/powernv/opal_console.c
head/sys/powerpc/powernv/opal_dev.c
head/sys/powerpc/powernv/opal_flash.c
head/sys/powerpc/powernv/opal_i2cm.c
head/sys/powerpc/powernv/opal_nvram.c
head/sys/powerpc/powernv/opal_pci.c
head/sys/powerpc/powernv/opal_sensor.c
head/sys/powerpc/powernv/platform_powernv.c
head/sys/powerpc/powernv/powernv_centaur.c
head/sys/powerpc/powernv/powernv_xscom.c
head/sys/powerpc/powernv/xive.c
head/sys/powerpc/powerpc/bus_machdep.c
head/sys/powerpc/powerpc/busdma_machdep.c
head/sys/powerpc/powerpc/clock.c
head/sys/powerpc/powerpc/copyinout.c
head/sys/powerpc/powerpc/cpu.c
head/sys/powerpc/powerpc/db_disasm.c
head/sys/powerpc/powerpc/db_interface.c
head/sys/powerpc/powerpc/db_trace.c
head/sys/powerpc/powerpc/elf32_machdep.c
head/sys/powerpc/powerpc/elf64_machdep.c
head/sys/powerpc/powerpc/exec_machdep.c
head/sys/powerpc/powerpc/genassym.c
head/sys/powerpc/powerpc/intr_machdep.c
head/sys/powerpc/powerpc/mem.c
head/sys/powerpc/powerpc/minidump_machdep.c
head/sys/powerpc/powerpc/mp_machdep.c
head/sys/powerpc/powerpc/nexus.c
head/sys/powerpc/powerpc/platform.c
head/sys/powerpc/powerpc/syncicache.c
head/sys/powerpc/powerpc/sys_machdep.c
head/sys/powerpc/powerpc/trap.c
head/sys/powerpc/powerpc/uma_machdep.c
head/sys/powerpc/ps3/if_glc.c
head/sys/powerpc/ps3/if_glcreg.h
head/sys/powerpc/ps3/mmu_ps3.c
head/sys/powerpc/ps3/ohci_ps3.c
head/sys/powerpc/ps3/platform_ps3.c
head/sys/powerpc/ps3/ps3_syscons.c
head/sys/powerpc/ps3/ps3bus.c
head/sys/powerpc/ps3/ps3cdrom.c
head/sys/powerpc/ps3/ps3disk.c
head/sys/powerpc/pseries/phyp-hvcall.h
head/sys/powerpc/pseries/phyp_console.c
head/sys/powerpc/pseries/phyp_dbg.c
head/sys/powerpc/pseries/phyp_llan.c
head/sys/powerpc/pseries/phyp_vscsi.c
head/sys/powerpc/pseries/platform_chrp.c
head/sys/powerpc/pseries/plpar_iommu.c
head/sys/powerpc/pseries/plpar_iommu.h
head/sys/powerpc/pseries/plpar_pcibus.c
head/sys/powerpc/pseries/rtas_dev.c
head/sys/powerpc/pseries/rtas_pci.c
head/sys/powerpc/pseries/vdevice.c
head/sys/powerpc/pseries/xics.c
head/sys/powerpc/psim/ata_iobus.c
head/sys/powerpc/psim/iobus.c
head/sys/powerpc/psim/openpic_iobus.c
head/sys/powerpc/psim/uart_iobus.c
Modified: head/sys/powerpc/aim/aim_machdep.c
==============================================================================
--- head/sys/powerpc/aim/aim_machdep.c Tue Sep 1 21:19:39 2020
(r365072)
+++ head/sys/powerpc/aim/aim_machdep.c Tue Sep 1 21:20:08 2020
(r365073)
@@ -391,7 +391,6 @@ aim_cpu_init(vm_offset_t toc)
bcopy(&restorebridge, (void *)EXC_TRC, trap_offset);
bcopy(&restorebridge, (void *)EXC_BPT, trap_offset);
} else {
-
/*
* Use an IBAT and a DBAT to map the bottom 256M segment.
*
@@ -572,7 +571,6 @@ cpu_machine_check(struct thread *td, struct trapframe
return (SIGBUS);
}
-
#ifndef __powerpc64__
uint64_t
va_to_vsid(pmap_t pm, vm_offset_t va)
@@ -779,4 +777,3 @@ cpu_sleep()
enable_vec(curthread);
powerpc_sync();
}
-
Modified: head/sys/powerpc/aim/mmu_oea.c
==============================================================================
--- head/sys/powerpc/aim/mmu_oea.c Tue Sep 1 21:19:39 2020
(r365072)
+++ head/sys/powerpc/aim/mmu_oea.c Tue Sep 1 21:20:08 2020
(r365073)
@@ -326,7 +326,6 @@ static int moea_map_user_ptr(pmap_t pm,
static int moea_decode_kernel_ptr(vm_offset_t addr,
int *is_user, vm_offset_t *decoded_addr);
-
static struct pmap_funcs moea_methods = {
.clear_modify = moea_clear_modify,
.copy_page = moea_copy_page,
@@ -1573,14 +1572,14 @@ moea_map_user_ptr(pmap_t pm, volatile const void *uadd
return (EFAULT);
vsid = va_to_vsid(pm, (vm_offset_t)uaddr);
-
+
/* Mark segment no-execute */
vsid |= SR_N;
-
+
/* If we have already set this VSID, we can just return */
if (curthread->td_pcb->pcb_cpu.aim.usr_vsid == vsid)
return (0);
-
+
__asm __volatile("isync");
curthread->td_pcb->pcb_cpu.aim.usr_segm =
(uintptr_t)uaddr >> ADDR_SR_SHFT;
@@ -1717,7 +1716,6 @@ moea_pinit(pmap_t pmap)
pmap->pmap_phys = pmap;
}
-
mtx_lock(&moea_vsid_mutex);
/*
* Allocate some segment registers for this pmap.
@@ -2481,7 +2479,6 @@ moea_query_bit(vm_page_t m, int ptebit)
return (TRUE);
LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
-
/*
* See if we saved the bit off. If so, cache it and return
* success.
@@ -2499,7 +2496,6 @@ moea_query_bit(vm_page_t m, int ptebit)
*/
powerpc_sync();
LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
-
/*
* See if this pvo has a valid PTE. if so, fetch the
* REF/CHG bits from the valid PTE. If the appropriate
Modified: head/sys/powerpc/aim/mmu_oea64.c
==============================================================================
--- head/sys/powerpc/aim/mmu_oea64.c Tue Sep 1 21:19:39 2020
(r365072)
+++ head/sys/powerpc/aim/mmu_oea64.c Tue Sep 1 21:20:08 2020
(r365073)
@@ -316,7 +316,6 @@ static void *moea64_dump_pmap_init(unsigned blkpgs);
static void moea64_page_array_startup(long);
#endif
-
static struct pmap_funcs moea64_methods = {
.clear_modify = moea64_clear_modify,
.copy_page = moea64_copy_page,
@@ -408,7 +407,6 @@ alloc_pvo_entry(int bootstrap)
return (pvo);
}
-
static void
init_pvo_entry(struct pvo_entry *pvo, pmap_t pmap, vm_offset_t va)
{
@@ -445,7 +443,7 @@ moea64_pte_from_pvo(const struct pvo_entry *pvo, struc
lpte->pte_hi = moea64_pte_vpn_from_pvo_vpn(pvo);
lpte->pte_hi |= LPTE_VALID;
-
+
if (pvo->pvo_vaddr & PVO_LARGE)
lpte->pte_hi |= LPTE_BIG;
if (pvo->pvo_vaddr & PVO_WIRED)
@@ -1688,7 +1686,7 @@ moea64_uma_page_alloc(uma_zone_t zone, vm_size_t bytes
if (needed_lock)
PMAP_UNLOCK(kernel_pmap);
-
+
if ((wait & M_ZERO) && (m->flags & PG_ZERO) == 0)
bzero((void *)va, PAGE_SIZE);
@@ -2373,7 +2371,6 @@ moea64_release_vsid(uint64_t vsid)
moea64_vsid_bitmap[idx] &= ~mask;
mtx_unlock(&moea64_slb_mutex);
}
-
void
moea64_release(pmap_t pmap)
Modified: head/sys/powerpc/aim/mmu_oea64.h
==============================================================================
--- head/sys/powerpc/aim/mmu_oea64.h Tue Sep 1 21:19:39 2020
(r365072)
+++ head/sys/powerpc/aim/mmu_oea64.h Tue Sep 1 21:20:08 2020
(r365073)
@@ -83,7 +83,6 @@ int64_t moea64_pte_unset(struct pvo_entry *);
int64_t moea64_pte_clear(struct pvo_entry *, uint64_t);
int64_t moea64_pte_synch(struct pvo_entry *);
-
typedef int64_t (*moea64_pte_replace_t)(struct pvo_entry *, int);
typedef int64_t (*moea64_pte_insert_t)(struct pvo_entry *);
typedef int64_t (*moea64_pte_unset_t)(struct pvo_entry *);
@@ -131,4 +130,3 @@ extern u_long moea64_pteg_mask;
extern int n_slbs;
#endif /* _POWERPC_AIM_MMU_OEA64_H */
-
Modified: head/sys/powerpc/aim/mmu_radix.c
==============================================================================
--- head/sys/powerpc/aim/mmu_radix.c Tue Sep 1 21:19:39 2020
(r365072)
+++ head/sys/powerpc/aim/mmu_radix.c Tue Sep 1 21:20:08 2020
(r365073)
@@ -25,11 +25,9 @@
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
-
#include <sys/param.h>
#include <sys/kernel.h>
#include <sys/systm.h>
@@ -597,8 +595,6 @@ static int pmap_change_attr_locked(vm_offset_t va, vm_
#define UNIMPLEMENTED() panic("%s not implemented", __func__)
#define UNTESTED() panic("%s not yet tested", __func__)
-
-
/* Number of supported PID bits */
static unsigned int isa3_pid_bits;
@@ -608,7 +604,6 @@ static unsigned int isa3_base_pid;
#define PROCTAB_SIZE_SHIFT (isa3_pid_bits + 4)
#define PROCTAB_ENTRIES (1ul << isa3_pid_bits)
-
/*
* Map of physical memory regions.
*/
@@ -712,7 +707,6 @@ static struct md_page pv_dummy;
*/
#define RTS_SIZE ((0x2UL << 61) | (0x5UL << 5))
-
static int powernv_enabled = 1;
static __always_inline void
@@ -846,7 +840,6 @@ pa_cmp(const void *a, const void *b)
#define PG_PTE_PROMOTE (PG_X | PG_MANAGED | PG_W | PG_PTE_CACHE | \
PG_M | PG_A | RPTE_EAA_MASK | PG_V)
-
static __inline void
pmap_resident_count_inc(pmap_t pmap, int count)
{
@@ -3069,7 +3062,6 @@ out:
return (rv);
}
-
/*
* Tries to create a read- and/or execute-only 2MB page mapping. Returns true
* if successful. Returns false if (1) a page table page cannot be allocated
@@ -4914,7 +4906,6 @@ pmap_demote_l3e_locked(pmap_t pmap, pml3_entry_t *l3e,
if ((oldpde & PG_MANAGED) != 0)
pmap_pv_demote_l3e(pmap, va, oldpde & PG_PS_FRAME, lockp);
-
atomic_add_long(&pmap_l3e_demotions, 1);
CTR2(KTR_PMAP, "pmap_demote_l3e: success for va %#lx"
" in pmap %p", va, pmap);
@@ -5000,7 +4991,6 @@ pmap_remove_l3e(pmap_t pmap, pml3_entry_t *pdq, vm_off
return (pmap_unuse_pt(pmap, sva, *pmap_pml2e(pmap, sva), free));
}
-
/*
* pmap_remove_pte: do the things to unmap a page in a process
*/
@@ -5103,7 +5093,6 @@ pmap_remove_ptes(pmap_t pmap, vm_offset_t sva, vm_offs
return (anyvalid);
}
-
void
mmu_radix_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
{
@@ -5147,7 +5136,6 @@ mmu_radix_remove(pmap_t pmap, vm_offset_t sva, vm_offs
lock = NULL;
for (; sva < eva; sva = va_next) {
-
if (pmap->pm_stats.resident_count == 0)
break;
l1e = pmap_pml1e(pmap, sva);
@@ -5683,9 +5671,6 @@ mmu_radix_zero_page_area(vm_page_t m, int off, int siz
memset(addr + off, 0, size);
}
-
-
-
static int
mmu_radix_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa)
{
@@ -6272,7 +6257,6 @@ pmap_change_attr_locked(vm_offset_t va, vm_size_t size
if (flush)
pmap_invalidate_cache_range(base, tmpva);
-
}
return (error);
}
@@ -6404,4 +6388,3 @@ DB_SHOW_COMMAND(pte, pmap_print_pte)
}
#endif
-
Modified: head/sys/powerpc/aim/moea64_native.c
==============================================================================
--- head/sys/powerpc/aim/moea64_native.c Tue Sep 1 21:19:39 2020
(r365072)
+++ head/sys/powerpc/aim/moea64_native.c Tue Sep 1 21:20:08 2020
(r365073)
@@ -282,7 +282,7 @@ moea64_pte_synch_native(struct pvo_entry *pvo)
ptelo = be64toh(pt->pte_lo);
rw_runlock(&moea64_eviction_lock);
-
+
return (ptelo & (LPTE_REF | LPTE_CHG));
}
Modified: head/sys/powerpc/aim/mp_cpudep.c
==============================================================================
--- head/sys/powerpc/aim/mp_cpudep.c Tue Sep 1 21:19:39 2020
(r365072)
+++ head/sys/powerpc/aim/mp_cpudep.c Tue Sep 1 21:20:08 2020
(r365073)
@@ -425,4 +425,3 @@ cpudep_ap_setup()
break;
}
}
-
Modified: head/sys/powerpc/aim/slb.c
==============================================================================
--- head/sys/powerpc/aim/slb.c Tue Sep 1 21:19:39 2020 (r365072)
+++ head/sys/powerpc/aim/slb.c Tue Sep 1 21:20:08 2020 (r365073)
@@ -100,7 +100,6 @@ esid2idx(uint64_t esid, int level)
#define uad_baseok(ua) \
(esid2base(ua->ua_base, ua->ua_level) == ua->ua_base)
-
static inline uint64_t
esid2base(uint64_t esid, int level)
{
@@ -561,7 +560,7 @@ handle_kernel_slb_spill(int type, register_t dar, regi
slbcache = PCPU_GET(aim.slb);
esid = (uintptr_t)addr >> ADDR_SR_SHFT;
slbe = (esid << SLBE_ESID_SHIFT) | SLBE_VALID;
-
+
/* See if the hardware flushed this somehow (can happen in LPARs) */
for (i = 0; i < n_slbs; i++)
if (slbcache[i].slbe == (slbe | (uint64_t)i))
Modified: head/sys/powerpc/amigaone/cpld_a1222.c
==============================================================================
--- head/sys/powerpc/amigaone/cpld_a1222.c Tue Sep 1 21:19:39 2020
(r365072)
+++ head/sys/powerpc/amigaone/cpld_a1222.c Tue Sep 1 21:20:08 2020
(r365073)
@@ -165,10 +165,10 @@ cpld_read_pair(struct cpld_softc *sc, int addr)
KASSERT(addr <= 0xff, ("Invalid register-pair base address %x.", addr));
bus_write_1(sc->sc_mem, CPLD_MEM_ADDR_H, addr);
tmp = bus_read_1(sc->sc_mem, CPLD_MEM_DATA) << 8;
-
+
bus_write_1(sc->sc_mem, CPLD_MEM_ADDR_H, addr + 1);
tmp |= bus_read_1(sc->sc_mem, CPLD_MEM_DATA);
-
+
return (tmp);
}
@@ -317,7 +317,7 @@ cpld_send(device_t dev, struct cpld_cmd_data *d)
if (d->cmd > USHRT_MAX)
return (EINVAL);
-
+
sc = device_get_softc(dev);
mtx_lock(&sc->sc_mutex);
Modified: head/sys/powerpc/amigaone/cpld_x5000.c
==============================================================================
--- head/sys/powerpc/amigaone/cpld_x5000.c Tue Sep 1 21:19:39 2020
(r365072)
+++ head/sys/powerpc/amigaone/cpld_x5000.c Tue Sep 1 21:20:08 2020
(r365073)
@@ -255,7 +255,7 @@ cpld_send(device_t dev, struct cpld_cmd_data *d)
if (d->cmd > USHRT_MAX)
return (EINVAL);
-
+
sc = device_get_softc(dev);
mtx_lock(&sc->sc_mutex);
Modified: head/sys/powerpc/booke/booke_machdep.c
==============================================================================
--- head/sys/powerpc/booke/booke_machdep.c Tue Sep 1 21:19:39 2020
(r365072)
+++ head/sys/powerpc/booke/booke_machdep.c Tue Sep 1 21:20:08 2020
(r365073)
@@ -360,7 +360,7 @@ booke_init(u_long arg1, u_long arg2)
* string 0x45504150 ('EPAP') in r6 (which has been lost by now).
* r4 (arg2) is supposed to be set to zero, but is not always.
*/
-
+
if (arg1 == 0) /* Juniper loader */
mdp = (void *)arg2;
else if (booke_check_for_fdt(arg1, &dtbp) == 0) { /* ePAPR */
@@ -471,4 +471,3 @@ kdb_cpu_set_singlestep(void)
mtspr(SPR_DBCR0, r | DBCR0_IC | DBCR0_IDM);
kdb_frame->srr1 |= PSL_DE;
}
-
Modified: head/sys/powerpc/booke/platform_bare.c
==============================================================================
--- head/sys/powerpc/booke/platform_bare.c Tue Sep 1 21:19:39 2020
(r365072)
+++ head/sys/powerpc/booke/platform_bare.c Tue Sep 1 21:20:08 2020
(r365073)
@@ -159,4 +159,3 @@ bare_reset(platform_t plat)
while (1)
;
}
-
Modified: head/sys/powerpc/booke/pmap.c
==============================================================================
--- head/sys/powerpc/booke/pmap.c Tue Sep 1 21:19:39 2020
(r365072)
+++ head/sys/powerpc/booke/pmap.c Tue Sep 1 21:20:08 2020
(r365073)
@@ -354,7 +354,6 @@ static int mmu_booke_decode_kernel_ptr(vm_offset_t
ad
static void mmu_booke_page_array_startup(long);
static boolean_t mmu_booke_page_is_mapped(vm_page_t m);
-
static struct pmap_funcs mmu_booke_methods = {
/* pmap dispatcher interface */
.clear_modify = mmu_booke_clear_modify,
@@ -475,7 +474,6 @@ tlb_miss_lock(void)
STAILQ_FOREACH(pc, &cpuhead, pc_allcpu) {
if (pc != pcpup) {
-
CTR3(KTR_PMAP, "%s: tlb miss LOCK of CPU=%d, "
"tlb_lock=%p", __func__, pc->pc_cpuid,
pc->pc_booke.tlb_lock);
@@ -561,7 +559,6 @@ pv_free(pv_entry_t pve)
uma_zfree(pvzone, pve);
}
-
/* Allocate and initialize pv_entry structure. */
static void
pv_insert(pmap_t pmap, vm_offset_t va, vm_page_t m)
@@ -842,7 +839,6 @@ mmu_booke_bootstrap(vm_offset_t start, vm_offset_t ker
debugf("fill in phys_avail:\n");
for (i = 0, j = 0; i < availmem_regions_sz; i++, j += 2) {
-
debugf(" region: 0x%jx - 0x%jx (0x%jx)\n",
(uintmax_t)availmem_regions[i].mr_start,
(uintmax_t)availmem_regions[i].mr_start +
@@ -930,7 +926,7 @@ mmu_booke_bootstrap(vm_offset_t start, vm_offset_t ker
(uintmax_t)kstack0_phys, (uintmax_t)kstack0_phys + kstack0_sz);
debugf("kstack0 at 0x%"PRI0ptrX" - 0x%"PRI0ptrX"\n",
kstack0, kstack0 + kstack0_sz);
-
+
virtual_avail += KSTACK_GUARD_PAGES * PAGE_SIZE + kstack0_sz;
for (i = 0; i < kstack_pages; i++) {
mmu_booke_kenter(kstack0, kstack0_phys);
@@ -939,7 +935,7 @@ mmu_booke_bootstrap(vm_offset_t start, vm_offset_t ker
}
pmap_bootstrapped = 1;
-
+
debugf("virtual_avail = %"PRI0ptrX"\n", virtual_avail);
debugf("virtual_end = %"PRI0ptrX"\n", virtual_end);
@@ -1034,7 +1030,7 @@ mmu_booke_kextract(vm_offset_t va)
if (va >= VM_MIN_KERNEL_ADDRESS && va <= VM_MAX_KERNEL_ADDRESS)
p = pte_vatopa(kernel_pmap, va);
-
+
if (p == 0) {
/* Check TLB1 mappings */
for (i = 0; i < TLB1_ENTRIES; i++) {
@@ -1148,9 +1144,8 @@ mmu_booke_kenter_attr(vm_offset_t va, vm_paddr_t pa, v
mtx_lock_spin(&tlbivax_mutex);
tlb_miss_lock();
-
+
if (PTE_ISVALID(pte)) {
-
CTR1(KTR_PMAP, "%s: replacing entry!", __func__);
/* Flush entry from TLB0 */
@@ -1188,7 +1183,6 @@ mmu_booke_kremove(vm_offset_t va)
pte = pte_find(kernel_pmap, va);
if (!PTE_ISVALID(pte)) {
-
CTR1(KTR_PMAP, "%s: invalid pte", __func__);
return;
@@ -1599,7 +1593,7 @@ mmu_booke_activate(struct thread *td)
cpuid = PCPU_GET(cpuid);
CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
PCPU_SET(curpmap, pmap);
-
+
if (pmap->pm_tid[cpuid] == TID_NONE)
tid_alloc(pmap);
@@ -1624,7 +1618,7 @@ mmu_booke_deactivate(struct thread *td)
pmap_t pmap;
pmap = &td->td_proc->p_vmspace->vm_pmap;
-
+
CTR5(KTR_PMAP, "%s: td=%p, proc = '%s', id = %d, pmap = 0x%"PRI0ptrX,
__func__, td, td->td_proc->p_comm, td->td_proc->p_pid, pmap);
@@ -2464,7 +2458,6 @@ tid_alloc(pmap_t pmap)
/* If we are stealing TID then clear the relevant pmap's field */
if (tidbusy[thiscpu][tid] != NULL) {
-
CTR2(KTR_PMAP, "%s: warning: stealing tid %d", __func__, tid);
tidbusy[thiscpu][tid]->pm_tid[thiscpu] = TID_NONE;
@@ -2516,7 +2509,6 @@ tlb0_flush_entry(vm_offset_t va)
CTR1(KTR_PMAP, "%s: e", __func__);
}
-
/**************************************************************************/
/* TLB1 handling */
/**************************************************************************/
@@ -2890,7 +2882,7 @@ pmap_early_io_map(vm_paddr_t pa, vm_size_t size)
tlb_entry_t e;
KASSERT(!pmap_bootstrapped, ("Do not use after PMAP is up!"));
-
+
for (i = 0; i < TLB1_ENTRIES; i++) {
tlb1_read_entry(&e, i);
if (!(e.mas1 & MAS1_VALID))
@@ -2943,7 +2935,6 @@ out:
rw_wunlock(&pvh_global_lock);
}
-
/*
* Setup MAS4 defaults.
* These values are loaded to MAS0-2 on a TLB miss.
@@ -2963,7 +2954,6 @@ set_mas4_defaults(void)
__asm __volatile("isync");
}
-
/*
* Return 0 if the physical IO range is encompassed by one of the
* the TLB1 entries, otherwise return related error code.
@@ -3068,7 +3058,6 @@ DB_SHOW_COMMAND(tlb0, tlb0_print_tlbentries)
printf("TLB0 entries:\n");
for (way = 0; way < TLB0_WAYS; way ++)
for (entryidx = 0; entryidx < TLB0_ENTRIES_PER_WAY; entryidx++)
{
-
mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(way);
mtspr(SPR_MAS0, mas0);
@@ -3102,7 +3091,6 @@ DB_SHOW_COMMAND(tlb1, tlb1_print_tlbentries)
printf("TLB1 entries:\n");
for (i = 0; i < TLB1_ENTRIES; i++) {
-
mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(i);
mtspr(SPR_MAS0, mas0);
Modified: head/sys/powerpc/booke/pmap_32.c
==============================================================================
--- head/sys/powerpc/booke/pmap_32.c Tue Sep 1 21:19:39 2020
(r365072)
+++ head/sys/powerpc/booke/pmap_32.c Tue Sep 1 21:20:08 2020
(r365073)
@@ -162,7 +162,6 @@ static struct ptbl_buf *ptbl_bufs;
/* Page table related */
/**************************************************************************/
-
/* Initialize pool of kva ptbl buffers. */
static void
ptbl_init(void)
@@ -323,7 +322,7 @@ ptbl_free(pmap_t pmap, unsigned int pdir_idx)
*/
mtx_lock_spin(&tlbivax_mutex);
tlb_miss_lock();
-
+
pmap->pm_pdir[pdir_idx] = NULL;
tlb_miss_unlock();
@@ -458,7 +457,6 @@ pte_remove(pmap_t pmap, vm_offset_t va, uint8_t flags)
/* Handle managed entry. */
if (PTE_ISMANAGED(pte)) {
-
if (PTE_ISMODIFIED(pte))
vm_page_dirty(m);
@@ -553,7 +551,7 @@ pte_enter(pmap_t pmap, vm_page_t m, vm_offset_t va, ui
}
pmap->pm_stats.resident_count++;
-
+
pte_tmp = PTE_RPN_FROM_PA(VM_PAGE_TO_PHYS(m));
pte_tmp |= (PTE_VALID | flags | PTE_PS_4KB); /* 4KB pages only */
@@ -735,7 +733,7 @@ mmu_booke_sync_icache(pmap_t pm, vm_offset_t va, vm_si
vm_page_t m;
vm_offset_t addr;
int active;
-
+
rw_wlock(&pvh_global_lock);
pmap = PCPU_GET(curpmap);
active = (pm == kernel_pmap || pm == pmap) ? 1 : 0;
@@ -950,7 +948,6 @@ tid_flush(tlbtid_t tid)
uint32_t mas0, mas1, mas2;
int entry, way;
-
/* Don't evict kernel translations */
if (tid == TID_KERNEL)
return;
@@ -975,7 +972,6 @@ tid_flush(tlbtid_t tid)
for (way = 0; way < TLB0_WAYS; way++)
for (entry = 0; entry < TLB0_ENTRIES_PER_WAY; entry++) {
-
mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(way);
mtspr(SPR_MAS0, mas0);
Modified: head/sys/powerpc/booke/pmap_64.c
==============================================================================
--- head/sys/powerpc/booke/pmap_64.c Tue Sep 1 21:19:39 2020
(r365072)
+++ head/sys/powerpc/booke/pmap_64.c Tue Sep 1 21:20:08 2020
(r365073)
@@ -408,7 +408,6 @@ pte_remove(pmap_t pmap, vm_offset_t va, u_int8_t flags
/* Handle managed entry. */
if (PTE_ISMANAGED(pte)) {
-
/* Handle modified pages. */
if (PTE_ISMODIFIED(pte))
vm_page_dirty(m);
@@ -519,7 +518,6 @@ pte_vatopa(pmap_t pmap, vm_offset_t va)
return (pa);
}
-
/* allocate pte entries to manage (addr & mask) to (addr & mask) + size */
static void
kernel_pte_alloc(vm_offset_t data_end, vm_offset_t addr)
@@ -590,7 +588,6 @@ mmu_booke_alloc_kernel_pgtables(vm_offset_t data_end)
return (data_end);
}
-
/*
* Initialize a preallocated and zeroed pmap structure,
* such as one in a vmspace structure.
@@ -645,7 +642,7 @@ mmu_booke_sync_icache(pmap_t pm, vm_offset_t va, vm_si
pte_t *pte;
vm_paddr_t pa = 0;
int sync_sz, valid;
-
+
while (sz > 0) {
PMAP_LOCK(pm);
pte = pte_find(pm, va);
Modified: head/sys/powerpc/booke/spe.c
==============================================================================
--- head/sys/powerpc/booke/spe.c Tue Sep 1 21:19:39 2020
(r365072)
+++ head/sys/powerpc/booke/spe.c Tue Sep 1 21:20:08 2020
(r365073)
@@ -197,7 +197,6 @@ save_vec_nodrop(struct thread *td)
}
}
-
#define SPE_INST_MASK 0x31f
#define EADD 0x200
#define ESUB 0x201
@@ -485,7 +484,7 @@ spe_handle_fpdata(struct trapframe *frame)
uint32_t msr;
err = fueword32((void *)frame->srr0, &instr);
-
+
if (err != 0)
return;
/* Fault. */;
Modified: head/sys/powerpc/cpufreq/dfs.c
==============================================================================
--- head/sys/powerpc/cpufreq/dfs.c Tue Sep 1 21:19:39 2020
(r365072)
+++ head/sys/powerpc/cpufreq/dfs.c Tue Sep 1 21:20:08 2020
(r365073)
@@ -62,7 +62,6 @@ static device_method_t dfs_methods[] = {
DEVMETHOD(cpufreq_drv_get, dfs_get),
DEVMETHOD(cpufreq_drv_type, dfs_type),
DEVMETHOD(cpufreq_drv_settings, dfs_settings),
-
{0, 0}
};
@@ -170,7 +169,7 @@ static int
dfs_set(device_t dev, const struct cf_setting *set)
{
register_t hid1;
-
+
if (set == NULL)
return (EINVAL);
@@ -181,7 +180,7 @@ dfs_set(device_t dev, const struct cf_setting *set)
hid1 |= HID1_DFS2;
else if (set->freq == 2500)
hid1 |= HID1_DFS4;
-
+
/*
* Now set the HID1 register with new values. Calling sequence
* taken from page 2-26 of the MPC7450 family CPU manual.
@@ -229,4 +228,3 @@ dfs_type(device_t dev, int *type)
*type = CPUFREQ_TYPE_RELATIVE;
return (0);
}
-
Modified: head/sys/powerpc/cpufreq/mpc85xx_jog.c
==============================================================================
--- head/sys/powerpc/cpufreq/mpc85xx_jog.c Tue Sep 1 21:19:39 2020
(r365072)
+++ head/sys/powerpc/cpufreq/mpc85xx_jog.c Tue Sep 1 21:20:08 2020
(r365073)
@@ -88,7 +88,6 @@ static device_method_t mpc85xx_jog_methods[] = {
DEVMETHOD(cpufreq_drv_get, mpc85xx_jog_get),
DEVMETHOD(cpufreq_drv_type, mpc85xx_jog_type),
DEVMETHOD(cpufreq_drv_settings, mpc85xx_jog_settings),
-
{0, 0}
};
@@ -154,7 +153,7 @@ mpc85xx_jog_identify(driver_t *driver, device_t parent
compat = mpc85xx_jog_devcompat();
if (compat == NULL)
return;
-
+
/*
* We attach a child for every CPU since settings need to
* be performed on every CPU in the SMP case.
@@ -200,7 +199,7 @@ mpc85xx_jog_attach(device_t dev)
OF_getencprop(cpu, "reg", &sc->cpu, sizeof(sc->cpu));
reg = ccsr_read4(GUTS_PORPLLSR);
-
+
/*
* Assume power-on PLL is the highest PLL config supported on the
* board.
@@ -290,7 +289,7 @@ mpc85xx_jog_set(device_t dev, const struct cf_setting
{
struct mpc85xx_jog_softc *sc;
struct jog_rv_args args;
-
+
if (set == NULL)
return (EINVAL);
@@ -323,7 +322,7 @@ mpc85xx_jog_get(device_t dev, struct cf_setting *set)
freq = PMJCR_GET_CORE_MULT(pmjcr, sc->cpu);
freq *= mpc85xx_get_system_clock();
freq /= MHZ;
-
+
set->freq = freq;
set->dev = dev;
@@ -340,4 +339,3 @@ mpc85xx_jog_type(device_t dev, int *type)
*type = CPUFREQ_TYPE_ABSOLUTE;
return (0);
}
-
Modified: head/sys/powerpc/cpufreq/pcr.c
==============================================================================
--- head/sys/powerpc/cpufreq/pcr.c Tue Sep 1 21:19:39 2020
(r365072)
+++ head/sys/powerpc/cpufreq/pcr.c Tue Sep 1 21:20:08 2020
(r365073)
@@ -65,7 +65,6 @@ static device_method_t pcr_methods[] = {
DEVMETHOD(cpufreq_drv_get, pcr_get),
DEVMETHOD(cpufreq_drv_type, pcr_type),
DEVMETHOD(cpufreq_drv_settings, pcr_settings),
-
{0, 0}
};
@@ -266,7 +265,7 @@ pcr_set(device_t dev, const struct cf_setting *set)
struct pcr_softc *sc;
register_t pcr, msr;
uint64_t psr;
-
+
if (set == NULL)
return (EINVAL);
sc = device_get_softc(dev);
@@ -342,4 +341,3 @@ pcr_type(device_t dev, int *type)
*type = CPUFREQ_TYPE_RELATIVE;
return (0);
}
-
Modified: head/sys/powerpc/cpufreq/pmcr.c
==============================================================================
--- head/sys/powerpc/cpufreq/pmcr.c Tue Sep 1 21:19:39 2020
(r365072)
+++ head/sys/powerpc/cpufreq/pmcr.c Tue Sep 1 21:20:08 2020
(r365073)
@@ -102,7 +102,6 @@ static device_method_t pmcr_methods[] = {
DEVMETHOD(cpufreq_drv_get, pmcr_get),
DEVMETHOD(cpufreq_drv_type, pmcr_type),
DEVMETHOD(cpufreq_drv_settings, pmcr_settings),
-
{0, 0}
};
@@ -186,7 +185,7 @@ static int
pmcr_set(device_t dev, const struct cf_setting *set)
{
register_t pmcr;
-
+
if (set == NULL)
return (EINVAL);
@@ -245,4 +244,3 @@ pmcr_type(device_t dev, int *type)
*type = CPUFREQ_TYPE_ABSOLUTE;
return (0);
}
-
Modified: head/sys/powerpc/cpufreq/pmufreq.c
==============================================================================
--- head/sys/powerpc/cpufreq/pmufreq.c Tue Sep 1 21:19:39 2020
(r365072)
+++ head/sys/powerpc/cpufreq/pmufreq.c Tue Sep 1 21:20:08 2020
(r365073)
@@ -70,7 +70,6 @@ static device_method_t pmufreq_methods[] = {
DEVMETHOD(cpufreq_drv_get, pmufreq_get),
DEVMETHOD(cpufreq_drv_type, pmufreq_type),
DEVMETHOD(cpufreq_drv_settings, pmufreq_settings),
-
{0, 0}
};
@@ -220,4 +219,3 @@ pmufreq_type(device_t dev, int *type)
*type = CPUFREQ_TYPE_ABSOLUTE;
return (0);
}
-
Modified: head/sys/powerpc/fpu/fpu_arith.h
==============================================================================
--- head/sys/powerpc/fpu/fpu_arith.h Tue Sep 1 21:19:39 2020
(r365072)
+++ head/sys/powerpc/fpu/fpu_arith.h Tue Sep 1 21:20:08 2020
(r365073)
@@ -57,7 +57,6 @@
* for example.
*/
-
#ifndef FPE_USE_ASM
/* set up for extended-precision arithemtic */
Modified: head/sys/powerpc/fpu/fpu_emu.c
==============================================================================
--- head/sys/powerpc/fpu/fpu_emu.c Tue Sep 1 21:19:39 2020
(r365072)
+++ head/sys/powerpc/fpu/fpu_emu.c Tue Sep 1 21:20:08 2020
(r365073)
@@ -179,7 +179,6 @@ fpu_dumpfpn(struct fpn *fp)
#define NOTFPU 2 /* not an FPU instruction */
#define FAULT 3
-
/*
* Emulate a floating-point instruction.
* Return zero for success, else signal number.
@@ -208,7 +207,6 @@ fpu_emulate(struct trapframe *frame, struct fpu *fpf)
DPRINTF(FPE_EX, ("fpu_emulate: emulating insn %x at %p\n",
insn.i_int, (void *)frame->srr0));
-
if ((insn.i_any.i_opcd == OPC_TWI) ||
((insn.i_any.i_opcd == OPC_integer_31) &&
(insn.i_x.i_xo == OPC31_TW))) {
@@ -314,7 +312,6 @@ fpu_execute(struct trapframe *tf, struct fpemu *fe, un
cond = 0; /* ld/st never set condition codes */
-
if (instr.i_any.i_opcd == OPC_integer_31) {
if (instr.i_x.i_xo == OPC31_STFIWX) {
FPU_EMU_EVCNT_INCR(stfiwx);
@@ -427,15 +424,12 @@ fpu_execute(struct trapframe *tf, struct fpemu *fe, un
#endif
} else if (instr.i_any.i_opcd == OPC_sp_fp_59 ||
instr.i_any.i_opcd == OPC_dp_fp_63) {
-
-
if (instr.i_any.i_opcd == OPC_dp_fp_63 &&
!(instr.i_a.i_xo & OPC63M_MASK)) {
/* Format X */
rt = instr.i_x.i_rt;
ra = instr.i_x.i_ra;
rb = instr.i_x.i_rb;
-
/* One of the special opcodes.... */
switch (instr.i_x.i_xo) {
Modified: head/sys/powerpc/fpu/fpu_explode.c
==============================================================================
--- head/sys/powerpc/fpu/fpu_explode.c Tue Sep 1 21:19:39 2020
(r365072)
+++ head/sys/powerpc/fpu/fpu_explode.c Tue Sep 1 21:20:08 2020
(r365073)
@@ -220,7 +220,6 @@ fpu_explode(struct fpemu *fe, struct fpn *fp, int type
fp->fp_sign = s >> 31;
fp->fp_sticky = 0;
switch (type) {
-
case FTYPE_LNG:
s = fpu_xtof(fp, l);
break;
Modified: head/sys/powerpc/fpu/fpu_extern.h
==============================================================================
--- head/sys/powerpc/fpu/fpu_extern.h Tue Sep 1 21:19:39 2020
(r365072)
+++ head/sys/powerpc/fpu/fpu_extern.h Tue Sep 1 21:20:08 2020
(r365073)
@@ -54,4 +54,3 @@ u_int fpu_ftoi(struct fpemu *, struct fpn *);
u_int fpu_ftox(struct fpemu *, struct fpn *, u_int *);
u_int fpu_ftos(struct fpemu *, struct fpn *);
u_int fpu_ftod(struct fpemu *, struct fpn *, u_int *);
-
Modified: head/sys/powerpc/fpu/fpu_implode.c
==============================================================================
--- head/sys/powerpc/fpu/fpu_implode.c Tue Sep 1 21:19:39 2020
(r365072)
+++ head/sys/powerpc/fpu/fpu_implode.c Tue Sep 1 21:20:08 2020
(r365073)
@@ -105,7 +105,6 @@ round(struct fpemu *fe, struct fpn *fp)
/* Go to rounddown to round down; break to round up. */
switch ((fe->fe_fpscr) & FPSCR_RN) {
-
case FP_RN:
default:
/*
@@ -169,7 +168,6 @@ toinf(struct fpemu *fe, int sign)
/* look at rounding direction */
switch ((fe->fe_fpscr) & FPSCR_RN) {
-
default:
case FP_RN: /* the nearest value is always Inf */
inf = 1;
@@ -206,7 +204,6 @@ fpu_ftoi(struct fpemu *fe, struct fpn *fp)
sign = fp->fp_sign;
switch (fp->fp_class) {
-
case FPC_ZERO:
return (0);
@@ -253,7 +250,6 @@ fpu_ftox(struct fpemu *fe, struct fpn *fp, u_int *res)
sign = fp->fp_sign;
switch (fp->fp_class) {
-
case FPC_ZERO:
res[1] = 0;
return (0);
@@ -432,7 +428,6 @@ fpu_implode(struct fpemu *fe, struct fpn *fp, int type
{
switch (type) {
-
case FTYPE_LNG:
space[0] = fpu_ftox(fe, fp, space);
DPRINTF(FPE_REG, ("fpu_implode: long %x %x\n",
Modified: head/sys/powerpc/fpu/fpu_instr.h
==============================================================================
--- head/sys/powerpc/fpu/fpu_instr.h Tue Sep 1 21:19:39 2020
(r365072)
+++ head/sys/powerpc/fpu/fpu_instr.h Tue Sep 1 21:20:08 2020
(r365073)
@@ -48,7 +48,7 @@
*/
union instr {
int i_int; /* as a whole */
-
+
/*
* Any instruction type.
*/
@@ -156,7 +156,6 @@ union instr {
u_int i_rc:1;
} i_mds;
-
/*
* Format S
*/
@@ -385,4 +384,3 @@ union instr {
#define FTYPE_INT 0 /* data = 32-bit signed integer */
#define FTYPE_SNG 1 /* data = 32-bit float */
#define FTYPE_DBL 2 /* data = 64-bit double */
-
Modified: head/sys/powerpc/include/altivec.h
==============================================================================
--- head/sys/powerpc/include/altivec.h Tue Sep 1 21:19:39 2020
(r365072)
+++ head/sys/powerpc/include/altivec.h Tue Sep 1 21:20:08 2020
(r365073)
@@ -39,4 +39,3 @@ void save_vec(struct thread *);
void save_vec_nodrop(struct thread *);
#endif /* _MACHINE_ALTIVEC_H_ */
-
Modified: head/sys/powerpc/include/atomic.h
==============================================================================
--- head/sys/powerpc/include/atomic.h Tue Sep 1 21:19:39 2020
(r365072)
+++ head/sys/powerpc/include/atomic.h Tue Sep 1 21:20:08 2020
(r365073)
@@ -228,7 +228,6 @@ _ATOMIC_ADD(long)
} \
/* _ATOMIC_CLEAR */
-
_ATOMIC_CLEAR(int)
_ATOMIC_CLEAR(long)
@@ -725,7 +724,6 @@ atomic_cmpset_long(volatile u_long* p, u_long cmpval,
ATOMIC_CMPSET_ACQ_REL(int);
ATOMIC_CMPSET_ACQ_REL(long);
-
#ifdef ISA_206_ATOMICS
#define atomic_cmpset_8 atomic_cmpset_char
Modified: head/sys/powerpc/include/bat.h
==============================================================================
--- head/sys/powerpc/include/bat.h Tue Sep 1 21:19:39 2020
(r365072)
+++ head/sys/powerpc/include/bat.h Tue Sep 1 21:20:08 2020
(r365073)
@@ -113,7 +113,6 @@ struct bat {
#define BATL(pa, wimg, pp)
\
(((pa) & BAT_PBS) | (wimg) | (pp))
-
/* Lower BAT bits (PowerPC 601): */
#define BAT601_PBN 0xfffe0000 /* physical block number */
#define BAT601_V 0x00000040 /* valid */
Modified: head/sys/powerpc/include/cpufunc.h
==============================================================================
--- head/sys/powerpc/include/cpufunc.h Tue Sep 1 21:19:39 2020
(r365072)
+++ head/sys/powerpc/include/cpufunc.h Tue Sep 1 21:20:08 2020
(r365073)
@@ -108,7 +108,6 @@ mfctrl(void)
return (value);
}
-
static __inline void
mtdec(register_t value)
{
Modified: head/sys/powerpc/include/mmuvar.h
==============================================================================
--- head/sys/powerpc/include/mmuvar.h Tue Sep 1 21:19:39 2020
(r365072)
+++ head/sys/powerpc/include/mmuvar.h Tue Sep 1 21:20:08 2020
(r365073)
@@ -200,7 +200,6 @@ extern mmu_t mmu_obj;
} while (mmu != NULL); \
f;})
-
#define MMU_DEF(name, ident, methods) \
\
const struct mmu_kobj name = { \
Modified: head/sys/powerpc/include/openpicreg.h
==============================================================================
--- head/sys/powerpc/include/openpicreg.h Tue Sep 1 21:19:39 2020
(r365072)
+++ head/sys/powerpc/include/openpicreg.h Tue Sep 1 21:20:08 2020
(r365073)
@@ -140,4 +140,3 @@
#define OPENPIC_PCPU_EOI(cpu) \
(OPENPIC_PCPU_BASE(cpu) + OPENPIC_EOI)
-
Modified: head/sys/powerpc/include/openpicvar.h
==============================================================================
--- head/sys/powerpc/include/openpicvar.h Tue Sep 1 21:19:39 2020
(r365072)
+++ head/sys/powerpc/include/openpicvar.h Tue Sep 1 21:20:08 2020
(r365073)
@@ -66,7 +66,7 @@ struct openpic_softc {
uint32_t sc_saved_prios[4];
struct openpic_timer sc_saved_timers[OPENPIC_TIMERS];
uint32_t sc_saved_vectors[OPENPIC_SRC_VECTOR_COUNT];
-
+
};
extern devclass_t openpic_devclass;
Modified: head/sys/powerpc/include/pcb.h
==============================================================================
--- head/sys/powerpc/include/pcb.h Tue Sep 1 21:19:39 2020
(r365072)
+++ head/sys/powerpc/include/pcb.h Tue Sep 1 21:20:08 2020
(r365073)
@@ -82,7 +82,7 @@ struct pcb {
uint64_t texasr;
uint64_t tfiar;
} pcb_htm;
-
+
struct ebb {
uint64_t ebbhr;
uint64_t ebbrr;
Modified: head/sys/powerpc/include/pio.h
==============================================================================
--- head/sys/powerpc/include/pio.h Tue Sep 1 21:19:39 2020
(r365072)
+++ head/sys/powerpc/include/pio.h Tue Sep 1 21:20:08 2020
(r365073)
@@ -178,7 +178,6 @@ __inlrb(volatile u_int32_t *a)
#define inlrb(a) (__inlrb((volatile u_int32_t *)(a)))
#define in32rb(a) inlrb(a)
-
static __inline void
__outsb(volatile u_int8_t *a, const u_int8_t *s, size_t c)
{
Modified: head/sys/powerpc/include/pmap.h
==============================================================================
--- head/sys/powerpc/include/pmap.h Tue Sep 1 21:19:39 2020
(r365072)
+++ head/sys/powerpc/include/pmap.h Tue Sep 1 21:20:08 2020
(r365073)
@@ -80,7 +80,6 @@
#include <vm/vm_radix.h>
#endif
-
/*
* The radix page table structure is described by levels 1-4.
* See Fig 33. on p. 1002 of Power ISA v3.0B
Modified: head/sys/powerpc/include/rtas.h
==============================================================================
--- head/sys/powerpc/include/rtas.h Tue Sep 1 21:19:39 2020
(r365072)
+++ head/sys/powerpc/include/rtas.h Tue Sep 1 21:20:08 2020
(r365073)
@@ -60,4 +60,3 @@ cell_t rtas_token_lookup(const char *method);
#define RTAS_VENDOR_ERROR_BEGIN -9004
*** DIFF OUTPUT TRUNCATED AT 1000 LINES ***
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