Author: adrian
Date: Tue Nov 27 02:18:41 2012
New Revision: 243588
URL: http://svnweb.freebsd.org/changeset/base/243588
Log:
When programming the beacon timer configuration, be very explicit about
what the maximum legal values are.
The current beacon timer configuration from TDMA wraps things at
HAL_BEACON_PERIOD-1 TU. For the 11a chips this is fine, but for
the 11n chips it's not enough resolution. Since the 11a chips have a
limit on what's "valid", just enforce this so when I do write larger
values in, they get suitably wrapped before programming.
Tested:
* AR5413, TDMA slave
Todo:
* Run it for a (lot) longer on a clear channel, ensure that no strange
slippages occur.
* Re-validate this on STA configurations, just to be sure.
Modified:
head/sys/dev/ath/ath_hal/ar5212/ar5212_beacon.c
Modified: head/sys/dev/ath/ath_hal/ar5212/ar5212_beacon.c
==============================================================================
--- head/sys/dev/ath/ath_hal/ar5212/ar5212_beacon.c Tue Nov 27 02:03:41
2012 (r243587)
+++ head/sys/dev/ath/ath_hal/ar5212/ar5212_beacon.c Tue Nov 27 02:18:41
2012 (r243588)
@@ -46,10 +46,19 @@ ar5212SetBeaconTimers(struct ath_hal *ah
{
struct ath_hal_5212 *ahp = AH5212(ah);
- OS_REG_WRITE(ah, AR_TIMER0, bt->bt_nexttbtt);
- OS_REG_WRITE(ah, AR_TIMER1, bt->bt_nextdba);
- OS_REG_WRITE(ah, AR_TIMER2, bt->bt_nextswba);
- OS_REG_WRITE(ah, AR_TIMER3, bt->bt_nextatim);
+ /*
+ * Limit the timers to their specific resolutions:
+ *
+ * + Timer 0 - 0..15 0xffff TU
+ * + Timer 1 - 0..18 0x7ffff TU/8
+ * + Timer 2 - 0..24 0x1ffffff TU/8
+ * + Timer 3 - 0..15 0xffff TU
+ */
+ OS_REG_WRITE(ah, AR_TIMER0, bt->bt_nexttbtt & 0xffff);
+ OS_REG_WRITE(ah, AR_TIMER1, bt->bt_nextdba & 0x7ffff);
+ OS_REG_WRITE(ah, AR_TIMER2, bt->bt_nextswba & 0x1ffffff);
+ /* XXX force nextatim to be non-zero? */
+ OS_REG_WRITE(ah, AR_TIMER3, bt->bt_nextatim & 0xffff);
/*
* Set the Beacon register after setting all timers.
*/
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