Author: adrian
Date: Wed Oct 9 00:27:12 2013
New Revision: 256172
URL: http://svnweb.freebsd.org/changeset/base/256172
Log:
Add "better" MIPS24k and MIPS74k barriers.
* the mips74k cores only need EHB (which is 'sll $0, $0, 3')
here; NOPs don't actually work.
* add EHB as the last NOP for the default barriers/hazards;
that is "better" behaviour and should work on a wider
variety of processors.
This allows the existing (icky) TLB code to work, allowing
the AR9344 SoC (mips74k) to actually get through kernel startup.
Tested:
* AR9344 SoC - (mips74k)
* AR9331 SoC - (mips24k)
TODO:
* test on mips4k CPUs, just to be sure.
* document that sll $0, $0, 3 is actually "EHB" and that it
falls back to being a NOP for pre-mips32r1.
* mips24k has an errata that we currently don't correctly explicitly
state - ie, that after DERET/ERET, the only valid instruction is
a NOP.
Reviewed by: imp@
Approved by: re@ (gjb)
Modified:
head/sys/mips/include/asm.h
head/sys/mips/include/cpuregs.h
Modified: head/sys/mips/include/asm.h
==============================================================================
--- head/sys/mips/include/asm.h Wed Oct 9 00:22:21 2013 (r256171)
+++ head/sys/mips/include/asm.h Wed Oct 9 00:27:12 2013 (r256172)
@@ -725,9 +725,12 @@ _C_LABEL(x):
#elif defined(CPU_RMI)
#define HAZARD_DELAY
#define ITLBNOPFIX
+#elif defined(CPU_MIPS74KC)
+#define HAZARD_DELAY sll $0,$0,3
+#define ITLBNOPFIX sll $0,$0,3
#else
-#define ITLBNOPFIX nop;nop;nop;nop;nop;nop;nop;nop;nop;nop;
-#define HAZARD_DELAY nop;nop;nop;nop;nop;
+#define ITLBNOPFIX nop;nop;nop;nop;nop;nop;nop;nop;nop;sll $0,$0,3;
+#define HAZARD_DELAY nop;nop;nop;nop;sll $0,$0,3;
#endif
#endif /* !_MACHINE_ASM_H_ */
Modified: head/sys/mips/include/cpuregs.h
==============================================================================
--- head/sys/mips/include/cpuregs.h Wed Oct 9 00:22:21 2013
(r256171)
+++ head/sys/mips/include/cpuregs.h Wed Oct 9 00:27:12 2013
(r256172)
@@ -149,6 +149,11 @@
#define MIPS_CCA_CC 0x05 /* Cacheable Coherent. */
#endif
+#if defined(CPU_MIPS74KC)
+#define MIPS_CCA_UNCACHED 0x02
+#define MIPS_CCA_CACHED 0x00
+#endif
+
#ifndef MIPS_CCA_UNCACHED
#define MIPS_CCA_UNCACHED MIPS_CCA_UC
#endif
@@ -204,12 +209,14 @@
#define COP0_SYNC .word 0xc0 /* ehb */
#elif defined(CPU_SB1)
#define COP0_SYNC ssnop; ssnop; ssnop; ssnop; ssnop; ssnop; ssnop; ssnop;
ssnop
+#elif defined(CPU_MIPS74KC)
+#define COP0_SYNC .word 0xc0 /* ehb */
#else
/*
* Pick a reasonable default based on the "typical" spacing described in the
* "CP0 Hazards" chapter of MIPS Architecture Book Vol III.
*/
-#define COP0_SYNC ssnop; ssnop; ssnop; ssnop; ssnop
+#define COP0_SYNC ssnop; ssnop; ssnop; ssnop; .word 0xc0;
#endif
#define COP0_HAZARD_FPUENABLE nop; nop; nop; nop;
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