Author: neel Date: Tue Dec 16 06:33:57 2014 New Revision: 275817 URL: https://svnweb.freebsd.org/changeset/base/275817
Log: For level triggered interrupts clear the PIC IRR bit when the interrupt pin is deasserted. Prior to this change each assertion on a level triggered irq pin resulted in two interrupts being delivered to the CPU. Differential Revision: https://reviews.freebsd.org/D1310 Reviewed by: tychon MFC after: 1 week Modified: head/sys/amd64/vmm/io/vatpic.c Modified: head/sys/amd64/vmm/io/vatpic.c ============================================================================== --- head/sys/amd64/vmm/io/vatpic.c Tue Dec 16 06:13:30 2014 (r275816) +++ head/sys/amd64/vmm/io/vatpic.c Tue Dec 16 06:33:57 2014 (r275817) @@ -388,6 +388,8 @@ vatpic_set_pinstate(struct vatpic *vatpi } else if (oldcnt == 1 && newcnt == 0) { /* falling edge */ VATPIC_CTR1(vatpic, "atpic pin%d: deasserted", pin); + if (level) + atpic->request &= ~(1 << (pin & 0x7)); } else { VATPIC_CTR3(vatpic, "atpic pin%d: %s, ignored, acnt %d", pin, newstate ? "asserted" : "deasserted", newcnt); _______________________________________________ [email protected] mailing list http://lists.freebsd.org/mailman/listinfo/svn-src-head To unsubscribe, send any mail to "[email protected]"
