Author: jhibbits
Date: Wed Feb 18 06:53:40 2015
New Revision: 278943
URL: https://svnweb.freebsd.org/changeset/base/278943
Log:
Don't set the write bit if we're just reading.
Also fix a couple typos.
MFC after: 3 weeks
Modified:
head/sys/powerpc/powermac/atibl.c
Modified: head/sys/powerpc/powermac/atibl.c
==============================================================================
--- head/sys/powerpc/powermac/atibl.c Wed Feb 18 06:26:07 2015
(r278942)
+++ head/sys/powerpc/powermac/atibl.c Wed Feb 18 06:53:40 2015
(r278943)
@@ -162,14 +162,13 @@ atibl_pll_rreg(struct atibl_softc *sc, u
{
uint32_t data, save, tmp;
- bus_write_1(sc->sc_memr, RADEON_CLOCK_CNTL_INDEX,
- ((reg & 0x3f) | RADEON_PLL_WR_EN));
+ bus_write_1(sc->sc_memr, RADEON_CLOCK_CNTL_INDEX, (reg & 0x3f));
(void)bus_read_4(sc->sc_memr, RADEON_CLOCK_CNTL_DATA);
(void)bus_read_4(sc->sc_memr, RADEON_CRTC_GEN_CNTL);
data = bus_read_4(sc->sc_memr, RADEON_CLOCK_CNTL_DATA);
- /* Only necessary on R300, bt won't hurt others. */
+ /* Only necessary on R300, but won't hurt others. */
save = bus_read_4(sc->sc_memr, RADEON_CLOCK_CNTL_INDEX);
tmp = save & (~0x3f | RADEON_PLL_WR_EN);
bus_write_4(sc->sc_memr, RADEON_CLOCK_CNTL_INDEX, tmp);
@@ -192,7 +191,7 @@ atibl_pll_wreg(struct atibl_softc *sc, u
bus_write_4(sc->sc_memr, RADEON_CLOCK_CNTL_DATA, val);
DELAY(5000);
- /* Only necessary on R300, bt won't hurt others. */
+ /* Only necessary on R300, but won't hurt others. */
save = bus_read_4(sc->sc_memr, RADEON_CLOCK_CNTL_INDEX);
tmp = save & (~0x3f | RADEON_PLL_WR_EN);
bus_write_4(sc->sc_memr, RADEON_CLOCK_CNTL_INDEX, tmp);
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