Author: jchandra
Date: Thu Feb 26 01:53:24 2015
New Revision: 279304
URL: https://svnweb.freebsd.org/changeset/base/279304

Log:
  Fix up interrupt definitions for Broadcom XLP
  
  Gather all the IRQ definitions to interrupt.h. Earlier these were in xlp.h
  and pic.h.  Update the definition of XLP_IRQ_IS_PICINTR to check for last
  irq as well.

Modified:
  head/sys/mips/nlm/hal/pic.h
  head/sys/mips/nlm/interrupt.h
  head/sys/mips/nlm/xlp.h

Modified: head/sys/mips/nlm/hal/pic.h
==============================================================================
--- head/sys/mips/nlm/hal/pic.h Wed Feb 25 22:41:27 2015        (r279303)
+++ head/sys/mips/nlm/hal/pic.h Thu Feb 26 01:53:24 2015        (r279304)
@@ -168,14 +168,9 @@
 #define        PIC_IRT_TIMER_INDEX(num)        ((num) + PIC_IRT_TIMER_0_INDEX)
 
 #define        PIC_CLOCK_TIMER                 7
-#define        PIC_IRQ_BASE                    8
 
 #if !defined(LOCORE) && !defined(__ASSEMBLY__)
 
-#define        PIC_IRT_FIRST_IRQ               (PIC_IRQ_BASE)
-#define        PIC_IRT_LAST_IRQ                63
-#define        XLP_IRQ_IS_PICINTR(irq)         ((irq) >= PIC_IRT_FIRST_IRQ)
-
 /*
  *   Misc
  */

Modified: head/sys/mips/nlm/interrupt.h
==============================================================================
--- head/sys/mips/nlm/interrupt.h       Wed Feb 25 22:41:27 2015        
(r279303)
+++ head/sys/mips/nlm/interrupt.h       Thu Feb 26 01:53:24 2015        
(r279304)
@@ -34,9 +34,22 @@
 
 /* Defines for the IRQ numbers */
 
-#define IRQ_IPI                        41  /* 8-39 are mapped by PIC intr 0-31 
*/
-#define IRQ_MSGRING             6
-#define IRQ_TIMER               7
+#define        IRQ_IPI                 41  /* 8-39 are used by PIC interrupts 
*/
+#define        IRQ_MSGRING             6
+#define        IRQ_TIMER               7
+
+#define        PIC_IRQ_BASE            8
+#define        PIC_IRT_LAST_IRQ        39
+#define        XLP_IRQ_IS_PICINTR(irq) ((irq) >= PIC_IRQ_BASE && \
+                                   (irq) <= PIC_IRT_LAST_IRQ)
+
+#define        PIC_UART_0_IRQ          9
+#define        PIC_PCIE_0_IRQ          11
+#define        PIC_PCIE_1_IRQ          12
+#define        PIC_PCIE_2_IRQ          13
+#define        PIC_PCIE_3_IRQ          14
+#define        PIC_EHCI_0_IRQ          16
+#define        PIC_MMC_IRQ             21
 
 /*
  * XLR needs custom pre and post handlers for PCI/PCI-e interrupts

Modified: head/sys/mips/nlm/xlp.h
==============================================================================
--- head/sys/mips/nlm/xlp.h     Wed Feb 25 22:41:27 2015        (r279303)
+++ head/sys/mips/nlm/xlp.h     Thu Feb 26 01:53:24 2015        (r279304)
@@ -34,18 +34,6 @@
 #include <mips/nlm/hal/mips-extns.h>
 #include <mips/nlm/hal/iomap.h>
 
-#define        PIC_UART_0_IRQ  9
-
-#define        PIC_PCIE_0_IRQ  11
-#define        PIC_PCIE_1_IRQ  12
-#define        PIC_PCIE_2_IRQ  13
-#define        PIC_PCIE_3_IRQ  14
-
-#define        PIC_EHCI_0_IRQ  16 
-#define        PIC_MMC_IRQ     21
-/* 41 used by IRQ_SMP */
-
-
 /* XLP 8xx/4xx A0, A1, A2 CPU COP0 PRIDs */
 #define        CHIP_PROCESSOR_ID_XLP_8XX               0x10
 #define        CHIP_PROCESSOR_ID_XLP_3XX               0x11
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