Author: andrew
Date: Sun Mar 29 20:37:28 2015
New Revision: 280823
URL: https://svnweb.freebsd.org/changeset/base/280823
Log:
Remove the bootconfig parsing. We never used it and always passed either an
empty string or NULL to the setup functions that called into it.
Deleted:
head/sys/arm/arm/bootconfig.c
head/sys/arm/include/bootconfig.h
Modified:
head/ObsoleteFiles.inc
head/sys/arm/arm/cpufunc.c
head/sys/arm/arm/machdep.c
head/sys/arm/arm/mp_machdep.c
head/sys/arm/at91/at91_machdep.c
head/sys/arm/cavium/cns11xx/econa_machdep.c
head/sys/arm/include/cpufunc.h
head/sys/arm/samsung/s3c2xx0/s3c24x0_machdep.c
head/sys/arm/xscale/i80321/ep80219_machdep.c
head/sys/arm/xscale/i80321/iq31244_machdep.c
head/sys/arm/xscale/i8134x/crb_machdep.c
head/sys/arm/xscale/ixp425/avila_machdep.c
head/sys/arm/xscale/pxa/pxa_machdep.c
head/sys/conf/files.arm
Modified: head/ObsoleteFiles.inc
==============================================================================
--- head/ObsoleteFiles.inc Sun Mar 29 20:28:18 2015 (r280822)
+++ head/ObsoleteFiles.inc Sun Mar 29 20:37:28 2015 (r280823)
@@ -38,6 +38,10 @@
# xargs -n1 | sort | uniq -d;
# done
+# 20150329
+.if ${TARGET_ARCH} == "arm"
+OLD_FILES+=usr/include/bootconfig.h
+.endif
# 20150326
OLD_FILES+=usr/share/man/man1/pmcstudy.1.gz
# 20150315: new clang import which bumps version from 3.5.1 to 3.6.0.
Modified: head/sys/arm/arm/cpufunc.c
==============================================================================
--- head/sys/arm/arm/cpufunc.c Sun Mar 29 20:28:18 2015 (r280822)
+++ head/sys/arm/arm/cpufunc.c Sun Mar 29 20:37:28 2015 (r280823)
@@ -59,7 +59,6 @@ __FBSDID("$FreeBSD$");
#include <machine/cpuconf.h>
#include <machine/cpufunc.h>
-#include <machine/bootconfig.h>
#ifdef CPU_XSCALE_80200
#include <arm/xscale/i80200/i80200reg.h>
@@ -1158,75 +1157,9 @@ cpufunc_null_fixup(arg)
* CPU Setup code
*/
-#if defined (CPU_ARM9) || \
- defined(CPU_ARM9E) || \
- defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
- defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \
- defined(CPU_XSCALE_80219) || defined(CPU_XSCALE_81342) || \
- defined(CPU_ARM1136) || defined(CPU_ARM1176) ||\
- defined(CPU_FA526) || defined(CPU_FA626TE)
-
-#define IGN 0
-#define OR 1
-#define BIC 2
-
-struct cpu_option {
- char *co_name;
- int co_falseop;
- int co_trueop;
- int co_value;
-};
-
-static u_int parse_cpu_options(char *, struct cpu_option *, u_int);
-
-static u_int
-parse_cpu_options(args, optlist, cpuctrl)
- char *args;
- struct cpu_option *optlist;
- u_int cpuctrl;
-{
- int integer;
-
- if (args == NULL)
- return(cpuctrl);
-
- while (optlist->co_name) {
- if (get_bootconf_option(args, optlist->co_name,
- BOOTOPT_TYPE_BOOLEAN, &integer)) {
- if (integer) {
- if (optlist->co_trueop == OR)
- cpuctrl |= optlist->co_value;
- else if (optlist->co_trueop == BIC)
- cpuctrl &= ~optlist->co_value;
- } else {
- if (optlist->co_falseop == OR)
- cpuctrl |= optlist->co_value;
- else if (optlist->co_falseop == BIC)
- cpuctrl &= ~optlist->co_value;
- }
- }
- ++optlist;
- }
- return(cpuctrl);
-}
-#endif /* CPU_ARM9 || XSCALE*/
-
#ifdef CPU_ARM9
-struct cpu_option arm9_options[] = {
- { "cpu.cache", BIC, OR, (CPU_CONTROL_IC_ENABLE |
CPU_CONTROL_DC_ENABLE) },
- { "cpu.nocache", OR, BIC, (CPU_CONTROL_IC_ENABLE |
CPU_CONTROL_DC_ENABLE) },
- { "arm9.cache", BIC, OR, (CPU_CONTROL_IC_ENABLE |
CPU_CONTROL_DC_ENABLE) },
- { "arm9.icache", BIC, OR, CPU_CONTROL_IC_ENABLE },
- { "arm9.dcache", BIC, OR, CPU_CONTROL_DC_ENABLE },
- { "cpu.writebuf", BIC, OR, CPU_CONTROL_WBUF_ENABLE },
- { "cpu.nowritebuf", OR, BIC, CPU_CONTROL_WBUF_ENABLE },
- { "arm9.writebuf", BIC, OR, CPU_CONTROL_WBUF_ENABLE },
- { NULL, IGN, IGN, 0 }
-};
-
void
-arm9_setup(args)
- char *args;
+arm9_setup(void)
{
int cpuctrl, cpuctrlmask;
@@ -1247,8 +1180,6 @@ arm9_setup(args)
cpuctrl |= CPU_CONTROL_AFLT_ENABLE;
#endif
- cpuctrl = parse_cpu_options(args, arm9_options, cpuctrl);
-
#ifdef __ARMEB__
cpuctrl |= CPU_CONTROL_BEND_ENABLE;
#endif
@@ -1266,21 +1197,8 @@ arm9_setup(args)
#endif /* CPU_ARM9 */
#if defined(CPU_ARM9E)
-struct cpu_option arm10_options[] = {
- { "cpu.cache", BIC, OR, (CPU_CONTROL_IC_ENABLE |
CPU_CONTROL_DC_ENABLE) },
- { "cpu.nocache", OR, BIC, (CPU_CONTROL_IC_ENABLE |
CPU_CONTROL_DC_ENABLE) },
- { "arm10.cache", BIC, OR, (CPU_CONTROL_IC_ENABLE |
CPU_CONTROL_DC_ENABLE) },
- { "arm10.icache", BIC, OR, CPU_CONTROL_IC_ENABLE },
- { "arm10.dcache", BIC, OR, CPU_CONTROL_DC_ENABLE },
- { "cpu.writebuf", BIC, OR, CPU_CONTROL_WBUF_ENABLE },
- { "cpu.nowritebuf", OR, BIC, CPU_CONTROL_WBUF_ENABLE },
- { "arm10.writebuf", BIC, OR, CPU_CONTROL_WBUF_ENABLE },
- { NULL, IGN, IGN, 0 }
-};
-
void
-arm10_setup(args)
- char *args;
+arm10_setup(void)
{
int cpuctrl, cpuctrlmask;
@@ -1298,8 +1216,6 @@ arm10_setup(args)
cpuctrl |= CPU_CONTROL_AFLT_ENABLE;
#endif
- cpuctrl = parse_cpu_options(args, arm10_options, cpuctrl);
-
#ifdef __ARMEB__
cpuctrl |= CPU_CONTROL_BEND_ENABLE;
#endif
@@ -1370,17 +1286,8 @@ cpu_scc_setup_ccnt(void)
#endif
#if defined(CPU_ARM1136) || defined(CPU_ARM1176)
-struct cpu_option arm11_options[] = {
- { "cpu.cache", BIC, OR, (CPU_CONTROL_IC_ENABLE |
CPU_CONTROL_DC_ENABLE) },
- { "cpu.nocache", OR, BIC, (CPU_CONTROL_IC_ENABLE |
CPU_CONTROL_DC_ENABLE) },
- { "arm11.cache", BIC, OR, (CPU_CONTROL_IC_ENABLE |
CPU_CONTROL_DC_ENABLE) },
- { "arm11.icache", BIC, OR, CPU_CONTROL_IC_ENABLE },
- { "arm11.dcache", BIC, OR, CPU_CONTROL_DC_ENABLE },
- { NULL, IGN, IGN, 0 }
-};
-
void
-arm11x6_setup(char *args)
+arm11x6_setup(void)
{
int cpuctrl, cpuctrl_wax;
uint32_t auxctrl, auxctrl_wax;
@@ -1415,8 +1322,6 @@ arm11x6_setup(char *args)
cpuctrl |= CPU_CONTROL_BPRD_ENABLE;
cpuctrl |= CPU_CONTROL_V6_EXTPAGE;
- cpuctrl = parse_cpu_options(args, arm11_options, cpuctrl);
-
#ifdef __ARMEB__
cpuctrl |= CPU_CONTROL_BEND_ENABLE;
#endif
@@ -1479,8 +1384,7 @@ arm11x6_setup(char *args)
#ifdef CPU_MV_PJ4B
void
-pj4bv7_setup(args)
- char *args;
+pj4bv7_setup(void)
{
int cpuctrl;
@@ -1516,7 +1420,7 @@ pj4bv7_setup(args)
#if defined(CPU_CORTEXA) || defined(CPU_KRAIT)
void
-cortexa_setup(char *args)
+cortexa_setup(void)
{
int cpuctrl, cpuctrlmask;
@@ -1563,23 +1467,8 @@ cortexa_setup(char *args)
#endif /* CPU_CORTEXA */
#if defined(CPU_FA526) || defined(CPU_FA626TE)
-struct cpu_option fa526_options[] = {
-#ifdef COMPAT_12
- { "nocache", IGN, BIC, (CPU_CONTROL_IC_ENABLE |
- CPU_CONTROL_DC_ENABLE) },
- { "nowritebuf", IGN, BIC, CPU_CONTROL_WBUF_ENABLE },
-#endif /* COMPAT_12 */
- { "cpu.cache", BIC, OR, (CPU_CONTROL_IC_ENABLE |
- CPU_CONTROL_DC_ENABLE) },
- { "cpu.nocache", OR, BIC, (CPU_CONTROL_IC_ENABLE |
- CPU_CONTROL_DC_ENABLE) },
- { "cpu.writebuf", BIC, OR, CPU_CONTROL_WBUF_ENABLE },
- { "cpu.nowritebuf", OR, BIC, CPU_CONTROL_WBUF_ENABLE },
- { NULL, IGN, IGN, 0 }
-};
-
void
-fa526_setup(char *args)
+fa526_setup(void)
{
int cpuctrl, cpuctrlmask;
@@ -1600,8 +1489,6 @@ fa526_setup(char *args)
cpuctrl |= CPU_CONTROL_AFLT_ENABLE;
#endif
- cpuctrl = parse_cpu_options(args, fa526_options, cpuctrl);
-
#ifdef __ARMEB__
cpuctrl |= CPU_CONTROL_BEND_ENABLE;
#endif
@@ -1621,24 +1508,8 @@ fa526_setup(char *args)
#if defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \
defined(CPU_XSCALE_80219) || defined(CPU_XSCALE_81342)
-struct cpu_option xscale_options[] = {
-#ifdef COMPAT_12
- { "branchpredict", BIC, OR, CPU_CONTROL_BPRD_ENABLE },
- { "nocache", IGN, BIC, (CPU_CONTROL_IC_ENABLE |
CPU_CONTROL_DC_ENABLE) },
-#endif /* COMPAT_12 */
- { "cpu.branchpredict", BIC, OR, CPU_CONTROL_BPRD_ENABLE },
- { "cpu.cache", BIC, OR, (CPU_CONTROL_IC_ENABLE |
CPU_CONTROL_DC_ENABLE) },
- { "cpu.nocache", OR, BIC, (CPU_CONTROL_IC_ENABLE |
CPU_CONTROL_DC_ENABLE) },
- { "xscale.branchpredict", BIC, OR, CPU_CONTROL_BPRD_ENABLE },
- { "xscale.cache", BIC, OR, (CPU_CONTROL_IC_ENABLE |
CPU_CONTROL_DC_ENABLE) },
- { "xscale.icache", BIC, OR, CPU_CONTROL_IC_ENABLE },
- { "xscale.dcache", BIC, OR, CPU_CONTROL_DC_ENABLE },
- { NULL, IGN, IGN, 0 }
-};
-
void
-xscale_setup(args)
- char *args;
+xscale_setup(void)
{
uint32_t auxctl;
int cpuctrl, cpuctrlmask;
@@ -1667,8 +1538,6 @@ xscale_setup(args)
cpuctrl |= CPU_CONTROL_AFLT_ENABLE;
#endif
- cpuctrl = parse_cpu_options(args, xscale_options, cpuctrl);
-
#ifdef __ARMEB__
cpuctrl |= CPU_CONTROL_BEND_ENABLE;
#endif
Modified: head/sys/arm/arm/machdep.c
==============================================================================
--- head/sys/arm/arm/machdep.c Sun Mar 29 20:28:18 2015 (r280822)
+++ head/sys/arm/arm/machdep.c Sun Mar 29 20:37:28 2015 (r280823)
@@ -1257,7 +1257,7 @@ initarm(struct arm_boot_params *abp)
* Now that proper page tables are installed, call cpu_setup() to enable
* instruction and data caches and other chip-specific features.
*/
- cpu_setup("");
+ cpu_setup();
/*
* Only after the SOC registers block is mapped we can perform device
@@ -1403,7 +1403,7 @@ initarm(struct arm_boot_params *abp)
* Now that proper page tables are installed, call cpu_setup() to enable
* instruction and data caches and other chip-specific features.
*/
- cpu_setup("");
+ cpu_setup();
/* Platform-specific initialisation */
platform_probe_and_attach();
Modified: head/sys/arm/arm/mp_machdep.c
==============================================================================
--- head/sys/arm/arm/mp_machdep.c Sun Mar 29 20:28:18 2015
(r280822)
+++ head/sys/arm/arm/mp_machdep.c Sun Mar 29 20:37:28 2015
(r280823)
@@ -155,14 +155,14 @@ init_secondary(int cpu)
#ifdef ARM_NEW_PMAP
pmap_set_tex();
reinit_mmu(pmap_kern_ttb, (1<<6) | (1<< 0), (1<<6) | (1<< 0));
- cpu_setup("");
+ cpu_setup();
/* Provide stack pointers for other processor modes. */
set_stackptrs(cpu);
enable_interrupts(PSR_A);
#else /* ARM_NEW_PMAP */
- cpu_setup(NULL);
+ cpu_setup();
setttb(pmap_pa);
cpu_tlb_flushID();
#endif /* ARM_NEW_PMAP */
Modified: head/sys/arm/at91/at91_machdep.c
==============================================================================
--- head/sys/arm/at91/at91_machdep.c Sun Mar 29 20:28:18 2015
(r280822)
+++ head/sys/arm/at91/at91_machdep.c Sun Mar 29 20:37:28 2015
(r280823)
@@ -606,7 +606,7 @@ initarm(struct arm_boot_params *abp)
* of the stack memory.
*/
cpu_control(CPU_CONTROL_MMU_ENABLE, CPU_CONTROL_MMU_ENABLE);
- cpu_setup("");
+ cpu_setup();
set_stackptrs(0);
Modified: head/sys/arm/cavium/cns11xx/econa_machdep.c
==============================================================================
--- head/sys/arm/cavium/cns11xx/econa_machdep.c Sun Mar 29 20:28:18 2015
(r280822)
+++ head/sys/arm/cavium/cns11xx/econa_machdep.c Sun Mar 29 20:37:28 2015
(r280823)
@@ -303,7 +303,7 @@ initarm(struct arm_boot_params *abp)
* this problem will not occur after initarm().
*/
cpu_idcache_wbinv_all();
- cpu_setup("");
+ cpu_setup();
undefined_init();
Modified: head/sys/arm/include/cpufunc.h
==============================================================================
--- head/sys/arm/include/cpufunc.h Sun Mar 29 20:28:18 2015
(r280822)
+++ head/sys/arm/include/cpufunc.h Sun Mar 29 20:37:28 2015
(r280823)
@@ -169,7 +169,7 @@ struct cpu_functions {
void (*cf_context_switch) (void);
- void (*cf_setup) (char *string);
+ void (*cf_setup) (void);
};
extern struct cpu_functions cpufuncs;
@@ -268,7 +268,7 @@ void tlb_broadcast(int);
#define ABORT_FIXUP_FAILED 1 /* fixup failed */
#define ABORT_FIXUP_RETURN 2 /* abort handler should return */
-#define cpu_setup(a) cpufuncs.cf_setup(a)
+#define cpu_setup() cpufuncs.cf_setup()
int set_cpufuncs (void);
#define ARCHITECTURE_NOT_PRESENT 1 /* known but not configured */
@@ -287,7 +287,7 @@ u_int cpufunc_faultaddress (void);
u_int cpu_pfr (int);
#if defined(CPU_FA526) || defined(CPU_FA626TE)
-void fa526_setup (char *arg);
+void fa526_setup (void);
void fa526_setttb (u_int ttb);
void fa526_context_switch (void);
void fa526_cpu_sleep (int);
@@ -325,7 +325,7 @@ void arm9_idcache_wbinv_range (vm_offset
void arm9_context_switch (void);
-void arm9_setup (char *string);
+void arm9_setup (void);
extern unsigned arm9_dcache_sets_max;
extern unsigned arm9_dcache_sets_inc;
@@ -339,7 +339,7 @@ void arm10_tlb_flushI_SE (u_int);
void arm10_context_switch (void);
-void arm10_setup (char *string);
+void arm10_setup (void);
u_int sheeva_control_ext (u_int, u_int);
void sheeva_cpu_sleep (int);
@@ -372,18 +372,18 @@ void armv7_dcache_wbinv_range (vm_offset
void armv7_dcache_inv_range (vm_offset_t, vm_size_t);
void armv7_dcache_wb_range (vm_offset_t, vm_size_t);
void armv7_cpu_sleep (int);
-void armv7_setup (char *string);
+void armv7_setup (void);
void armv7_context_switch (void);
void armv7_drain_writebuf (void);
void armv7_sev (void);
void armv7_sleep (int unused);
u_int armv7_auxctrl (u_int, u_int);
-void pj4bv7_setup (char *string);
+void pj4bv7_setup (void);
void pj4b_config (void);
void armadaxp_idcache_wbinv_all (void);
-void cortexa_setup (char *);
+void cortexa_setup (void);
#endif
#if defined(CPU_ARM1136) || defined(CPU_ARM1176)
@@ -411,7 +411,7 @@ void arm11x6_icache_sync_all
void arm11x6_flush_prefetchbuf (void);
void arm11x6_icache_sync_range (vm_offset_t, vm_size_t);
void arm11x6_idcache_wbinv_range (vm_offset_t, vm_size_t);
-void arm11x6_setup (char *string);
+void arm11x6_setup (void);
void arm11x6_sleep (int); /* no ref. for errata */
#endif
#if defined(CPU_ARM1136)
@@ -488,7 +488,7 @@ void xscale_cache_flushD_rng (vm_offset_
void xscale_context_switch (void);
-void xscale_setup (char *string);
+void xscale_setup (void);
#endif /* CPU_XSCALE_80200 || CPU_XSCALE_80321 || CPU_XSCALE_PXA2X0 ||
CPU_XSCALE_IXP425
CPU_XSCALE_80219 */
Modified: head/sys/arm/samsung/s3c2xx0/s3c24x0_machdep.c
==============================================================================
--- head/sys/arm/samsung/s3c2xx0/s3c24x0_machdep.c Sun Mar 29 20:28:18
2015 (r280822)
+++ head/sys/arm/samsung/s3c2xx0/s3c24x0_machdep.c Sun Mar 29 20:37:28
2015 (r280823)
@@ -350,7 +350,7 @@ initarm(struct arm_boot_params *abp)
* this problem will not occur after initarm().
*/
cpu_idcache_wbinv_all();
- cpu_setup("");
+ cpu_setup();
/* Disable all peripheral interrupts */
ioreg_write32(S3C24X0_INTCTL_BASE + INTCTL_INTMSK, ~0);
Modified: head/sys/arm/xscale/i80321/ep80219_machdep.c
==============================================================================
--- head/sys/arm/xscale/i80321/ep80219_machdep.c Sun Mar 29 20:28:18
2015 (r280822)
+++ head/sys/arm/xscale/i80321/ep80219_machdep.c Sun Mar 29 20:37:28
2015 (r280823)
@@ -305,7 +305,7 @@ initarm(struct arm_boot_params *abp)
* this problem will not occur after initarm().
*/
cpu_idcache_wbinv_all();
- cpu_setup("");
+ cpu_setup();
/*
* Fetch the SDRAM start/size from the i80321 SDRAM configration
Modified: head/sys/arm/xscale/i80321/iq31244_machdep.c
==============================================================================
--- head/sys/arm/xscale/i80321/iq31244_machdep.c Sun Mar 29 20:28:18
2015 (r280822)
+++ head/sys/arm/xscale/i80321/iq31244_machdep.c Sun Mar 29 20:37:28
2015 (r280823)
@@ -306,7 +306,7 @@ initarm(struct arm_boot_params *abp)
* this problem will not occur after initarm().
*/
cpu_idcache_wbinv_all();
- cpu_setup("");
+ cpu_setup();
/*
* Fetch the SDRAM start/size from the i80321 SDRAM configration
Modified: head/sys/arm/xscale/i8134x/crb_machdep.c
==============================================================================
--- head/sys/arm/xscale/i8134x/crb_machdep.c Sun Mar 29 20:28:18 2015
(r280822)
+++ head/sys/arm/xscale/i8134x/crb_machdep.c Sun Mar 29 20:37:28 2015
(r280823)
@@ -290,7 +290,7 @@ initarm(struct arm_boot_params *abp)
* this problem will not occur after initarm().
*/
cpu_idcache_wbinv_all();
- cpu_setup("");
+ cpu_setup();
i80321_calibrate_delay();
i81342_sdram_bounds(obio_bs_tag, IOP34X_VADDR, &memstart, &memsize);
Modified: head/sys/arm/xscale/ixp425/avila_machdep.c
==============================================================================
--- head/sys/arm/xscale/ixp425/avila_machdep.c Sun Mar 29 20:28:18 2015
(r280822)
+++ head/sys/arm/xscale/ixp425/avila_machdep.c Sun Mar 29 20:37:28 2015
(r280823)
@@ -376,7 +376,7 @@ initarm(struct arm_boot_params *abp)
* this problem will not occur after initarm().
*/
cpu_idcache_wbinv_all();
- cpu_setup("");
+ cpu_setup();
/* ready to setup the console (XXX move earlier if possible) */
cninit();
Modified: head/sys/arm/xscale/pxa/pxa_machdep.c
==============================================================================
--- head/sys/arm/xscale/pxa/pxa_machdep.c Sun Mar 29 20:28:18 2015
(r280822)
+++ head/sys/arm/xscale/pxa/pxa_machdep.c Sun Mar 29 20:37:28 2015
(r280823)
@@ -291,7 +291,7 @@ initarm(struct arm_boot_params *abp)
* this problem will not occur after initarm().
*/
cpu_idcache_wbinv_all();
- cpu_setup("");
+ cpu_setup();
/*
* Sort out bus_space for on-board devices.
Modified: head/sys/conf/files.arm
==============================================================================
--- head/sys/conf/files.arm Sun Mar 29 20:28:18 2015 (r280822)
+++ head/sys/conf/files.arm Sun Mar 29 20:37:28 2015 (r280823)
@@ -3,7 +3,6 @@ arm/arm/autoconf.c standard
arm/arm/bcopy_page.S standard
arm/arm/bcopyinout.S standard
arm/arm/blockio.S standard
-arm/arm/bootconfig.c standard
arm/arm/bus_space_asm_generic.S standard
arm/arm/busdma_machdep.c optional !armv6
arm/arm/busdma_machdep-v6.c optional armv6
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