Author: neel Date: Wed May 6 05:12:29 2015 New Revision: 282519 URL: https://svnweb.freebsd.org/changeset/base/282519
Log: Add macros for AMD-specific bits in MSR_EFER: LMSLE, FFXSR and TCE. AMDID_FFXSR is at bit 25 so correct its value to 0x02000000. MFC after: 1 week Modified: head/sys/x86/include/specialreg.h Modified: head/sys/x86/include/specialreg.h ============================================================================== --- head/sys/x86/include/specialreg.h Wed May 6 01:29:31 2015 (r282518) +++ head/sys/x86/include/specialreg.h Wed May 6 05:12:29 2015 (r282519) @@ -82,6 +82,9 @@ #define EFER_LMA 0x000000400 /* Long mode active (R) */ #define EFER_NXE 0x000000800 /* PTE No-Execute bit enable (R/W) */ #define EFER_SVM 0x000001000 /* SVM enable bit for AMD, reserved for Intel */ +#define EFER_LMSLE 0x000002000 /* Long Mode Segment Limit Enable */ +#define EFER_FFXSR 0x000004000 /* Fast FXSAVE/FSRSTOR */ +#define EFER_TCE 0x000008000 /* Translation Cache Extension */ /* * Intel Extended Features registers @@ -191,7 +194,7 @@ #define AMDID_MP 0x00080000 #define AMDID_NX 0x00100000 #define AMDID_EXT_MMX 0x00400000 -#define AMDID_FFXSR 0x01000000 +#define AMDID_FFXSR 0x02000000 #define AMDID_PAGE1GB 0x04000000 #define AMDID_RDTSCP 0x08000000 #define AMDID_LM 0x20000000 _______________________________________________ [email protected] mailing list http://lists.freebsd.org/mailman/listinfo/svn-src-head To unsubscribe, send any mail to "[email protected]"
