Author: adrian Date: Fri Jul 3 03:32:54 2015 New Revision: 285072 URL: https://svnweb.freebsd.org/changeset/base/285072
Log: Add register defines for the QCA955x DDR flush and GPIO control. Modified: head/sys/mips/atheros/qca955xreg.h Modified: head/sys/mips/atheros/qca955xreg.h ============================================================================== --- head/sys/mips/atheros/qca955xreg.h Fri Jul 3 02:06:47 2015 (r285071) +++ head/sys/mips/atheros/qca955xreg.h Fri Jul 3 03:32:54 2015 (r285072) @@ -179,6 +179,13 @@ #define QCA955X_RESET_I2S BIT(0) /* GPIO block */ +#define QCA955X_GPIO_REG_OUT_FUNC0 0x2c +#define QCA955X_GPIO_REG_OUT_FUNC1 0x30 +#define QCA955X_GPIO_REG_OUT_FUNC2 0x34 +#define QCA955X_GPIO_REG_OUT_FUNC3 0x38 +#define QCA955X_GPIO_REG_OUT_FUNC4 0x3c +#define QCA955X_GPIO_REG_OUT_FUNC5 0x40 +#define QCA955X_GPIO_REG_FUNC 0x6c #define QCA955X_GPIO_COUNT 24 #define QCA955X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000) @@ -204,6 +211,10 @@ #define QCA955X_DDR_REG_FLUSH_USB (AR71XX_APB_BASE + 0xa4) #define QCA955X_DDR_REG_FLUSH_PCIE (AR71XX_APB_BASE + 0xa8) #define QCA955X_DDR_REG_FLUSH_WMAC (AR71XX_APB_BASE + 0xac) +/* PCIe EP */ +#define QCA955X_DDR_REG_FLUSH_SRC1 (AR71XX_APB_BSAE + 0xb0) +/* checksum engine */ +#define QCA955X_DDR_REG_FLUSH_SRC2 (AR71XX_APB_BSAE + 0xb2) /* PCIe control block - relative to PCI_CTRL_BASE0/PCI_CTRL_BASE1 */ _______________________________________________ [email protected] mailing list http://lists.freebsd.org/mailman/listinfo/svn-src-head To unsubscribe, send any mail to "[email protected]"
