On Monday, December 14, 2015 04:07:20 PM Andrew Turner wrote: > Author: andrew > Date: Mon Dec 14 16:07:20 2015 > New Revision: 292214 > URL: https://svnweb.freebsd.org/changeset/base/292214 > > Log: > Add support for MSI interrupts to the gicv2m controller. The allocation > is still quite simplistic, it just increments a counter to use the next > interrupt. > > Obtained from: ABT Systems Ltd > Sponsored by: SoftIron Inc
Does this work for a count > 1? With MSI (but not MSI-X) when you have a count > 1, you typically need an aligned, contiguous block of vectors. In particular, for MSI you can only request a power of 2 number of messages. The low N bits (where N == log base 2 of 'count') of the resulting 'data' register value (from PCIB_MAP_MSI()) must be zero for the first message in the block. When the PCI function wants to send a message, it stores the message index (i.e. which MSI message) in the low N bits). On x86 the low 8 bits of the data message are the IDT vector, so this means that MSI message blocks require an aligned, contiguous block of IDT vectors on the destination CPU. MSI-X avoids this need by providing separate address/data register pairs for each message, so each message can use an arbitrary vector. You do seem to use a contiguous block of vectors, but it's not clear they are aligned? -- John Baldwin _______________________________________________ [email protected] mailing list https://lists.freebsd.org/mailman/listinfo/svn-src-head To unsubscribe, send any mail to "[email protected]"
