Author: adrian Date: Thu Dec 24 18:31:55 2015 New Revision: 292699 URL: https://svnweb.freebsd.org/changeset/base/292699
Log: [rt305x] add register space definitions for later generation chips. This adds definitions for the MT5350 and MT7620 SoCs. Submitted by: Stanislav Galabov <gala...@gmail.com> Modified: head/sys/mips/rt305x/rt305xreg.h Modified: head/sys/mips/rt305x/rt305xreg.h ============================================================================== --- head/sys/mips/rt305x/rt305xreg.h Thu Dec 24 18:30:04 2015 (r292698) +++ head/sys/mips/rt305x/rt305xreg.h Thu Dec 24 18:31:55 2015 (r292699) @@ -1,4 +1,5 @@ /*- + * Copyright (c) 2015 Stanislav Galabov. * Copyright (c) 2010 Aleksandr Rybalko. * All rights reserved. * @@ -29,12 +30,7 @@ #ifndef _RT305XREG_H_ #define _RT305XREG_H_ -/* XXX: must move to config */ -#define RT305X 1 -#define RT305XF 1 -#define RT3052F 1 -#define __U_BOOT__ 1 -/* XXX: must move to config */ +#include "opt_rt305x.h" #ifdef RT3052F #define PLATFORM_COUNTER_FREQ (384 * 1000 * 1000) @@ -42,12 +38,19 @@ #ifdef RT3050F #define PLATFORM_COUNTER_FREQ (320 * 1000 * 1000) #endif +#ifdef MT7620 +#define PLATFORM_COUNTER_FREQ (580 * 1000 * 1000) +#endif +#ifdef RT5350 +#define PLATFORM_COUNTER_FREQ (360 * 1000 * 1000) +#endif #ifndef PLATFORM_COUNTER_FREQ -#error "Nor RT3052F nor RT3050F defined" +#error "No platform selected" #endif -#define SYSTEM_CLOCK (PLATFORM_COUNTER_FREQ/3) +#ifndef MT7620 +#define SYSTEM_CLOCK (PLATFORM_COUNTER_FREQ/3) #define SDRAM_BASE 0x00000000 #define SDRAM_END 0x03FFFFFF @@ -60,16 +63,26 @@ #define INTCTL_END 0x100002FF #define MEMCTRL_BASE 0x10000300 #define MEMCTRL_END 0x100003FF /* SDRAM & Flash/SRAM */ +#ifndef RT5350 #define PCM_BASE 0x10000400 #define PCM_END 0x100004FF +#else +#define PCM_BASE 0x10002000 +#define PCM_END 0x100027FF +#endif #define UART_BASE 0x10000500 #define UART_END 0x100005FF #define PIO_BASE 0x10000600 #define PIO_END 0x100006FF +#ifndef RT5350 #define GDMA_BASE 0x10000700 #define GDMA_END 0x100007FF /* Generic DMA */ #define NANDFC_BASE 0x10000800 #define NANDFC_END 0x100008FF /* NAND Flash Controller */ +#else +#define GDMA_BASE 0x10002800 +#define GDMA_END 0x10002FFF +#endif #define I2C_BASE 0x10000900 #define I2C_END 0x100009FF #define I2S_BASE 0x10000A00 @@ -87,23 +100,110 @@ #define ROM_END 0x10119FFF #define WLAN_BASE 0x10180000 #define WLAN_END 0x101BFFFF /* 802.11n MAC/BBP */ +#ifndef RT5350 #define USB_OTG_BASE 0x101C0000 #define USB_OTG_END 0x101FFFFF +#else +#define USB_OTG_BASE 0x101C0000 +#define USB_OTG_END 0x101C0FFF +#define USB_OHCI_BASE 0x101C1000 +#define USB_OHCI_END 0x101C1FFF +#endif #define EMEM_BASE 0x1B000000 #define EMEM_END 0x1BFFFFFF /* External SRAM/Flash */ +#ifdef RT5350 +#define BOOT_ROM_BASE 0x1C000000 +#define BOOT_ROM_END 0x1C003FFF +#endif +#ifndef RT5350 #define FLASH_BASE 0x1F000000 #define FLASH_END 0x1FFFFFFF /* Flash window */ +#endif #define OBIO_MEM_BASE SYSCTL_BASE #define OBIO_MEM_START OBIO_MEM_BASE +#ifndef RT5350 #define OBIO_MEM_END FLASH_END +#else +#define OBIO_MEM_END BOOT_ROM_END +#endif + +#else /* MT7620 */ +#define SYSTEM_CLOCK (40 * 1000 * 1000) +#define SDRAM_BASE 0x00000000 +#define SDRAM_END 0x0FFFFFFF + +#define SYSCTL_BASE 0x10000000 +#define SYSCTL_END 0x100000FF +#define TIMER_BASE 0x10000100 +#define TIMER_END 0x100001FF +#define INTCTL_BASE 0x10000200 +#define INTCTL_END 0x100002FF +#define MEMCTRL_BASE 0x10000300 +#define MEMCTRL_END 0x100003FF /* SDRAM & Flash/SRAM */ +#define PCM_BASE 0x10002000 +#define PCM_END 0x100027FF +#define UART_BASE 0x10000500 +#define UART_END 0x100005FF +#define PIO_BASE 0x10000600 +#define PIO_END 0x100006FF +#define GDMA_BASE 0x10002800 +#define GDMA_END 0x10002FFF /* Generic DMA */ +#define NANDFC_BASE 0x10000800 +#define NANDFC_END 0x100008FF /* NAND Flash Controller */ +#define I2C_BASE 0x10000900 +#define I2C_END 0x100009FF +#define I2S_BASE 0x10000A00 +#define I2S_END 0x10000AFF +#define SPI_BASE 0x10000B00 +#define SPI_END 0x10000BFF +#define UARTLITE_BASE 0x10000C00 +#define UARTLITE_END 0x10000CFF + +#define FRENG_BASE 0x10100000 +#define FRENG_END 0x1010FFFF /* Frame Engine */ +#define ETHSW_BASE 0x10110000 +#define ETHSW_END 0x10117FFF /* Ethernet Switch */ +#define ROM_BASE 0x10118000 +#define ROM_END 0x1011FFFF +#define WLAN_BASE 0x10180000 +#define WLAN_END 0x101BFFFF /* 802.11n MAC/BBP */ +#define USB_OTG_BASE 0x101C0000 +#define USB_OTG_END 0x101C0FFF +#define USB_OHCI_BASE 0x101C1000 +#define USB_OHCI_END 0x101C1FFF +#define PCIE_BASE 0x10140000 +#define PCIE_END 0x1017FFFF +#define SDHC_BASE 0x10130000 +#define SDHC_END 0x10133FFF + +#define PCIE_IO_BASE 0x10160000 +#define PCIE_IO_END 0x1016FFFF +#define PCIE_MEM_BASE 0x20000000 +#define PCIE_MEM_END 0x2FFFFFFF + +// TODO: fix below mappings? +#define EMEM_BASE 0x1B000000 +#define EMEM_END 0x1BFFFFFF /* External SRAM/Flash */ +#define FLASH_BASE 0x1F000000 +#define FLASH_END 0x1FFFFFFF /* Flash window */ + +#define OBIO_MEM_BASE SYSCTL_BASE +#define OBIO_MEM_START OBIO_MEM_BASE +#define OBIO_MEM_END FLASH_END +#endif /* System Control */ -#define SYSCTL_CHIPID0_3 0x00 /* 'R''T''3''0' */ -#define SYSCTL_CHIPID4_7 0x04 /* '5''2'' '' ' */ +#define SYSCTL_CHIPID0_3 0x00 +#define SYSCTL_CHIPID4_7 0x04 +#ifdef RT5350 +#define SYSCTL_REVID 0x0C +#endif + #define SYSCTL_SYSCFG 0x10 +#if !defined(RT5350) && !defined(MT7620) #define SYSCTL_SYSCFG_INIC_EE_SDRAM (1<<29) #define SYSCTL_SYSCFG_INIC_8MB_SDRAM (1<<28) #define SYSCTL_SYSCFG_GE0_MODE_MASK 0x03000000 @@ -129,6 +229,18 @@ #define SYSCTL_SYSCFG_SRAM_CS_MODE_WDOG_RST 1 #define SYSCTL_SYSCFG_SRAM_CS_MODE_BT_COEX 2 #define SYSCTL_SYSCFG_SDRAM_CLK_DRV (1<<0) /* 8mA/12mA */ +#endif +#ifdef RT5350 +#define SYSCTL1_SYSCFG_PULL_EN (1<<26) +#define SYSCTL1_SYSCFG_SDR_PAD_DRV_MASK 0x0700000 +#define SYSCTL1_SYSCFG_SDR_PAD_DRV_SHIFT 20 +#define SYSCTL1_SYSCFG_SDR_PAD_DRV_0 0 +#define SYSCTL1_SYSCFG_SDR_PAD_DRV_1 1 +#define SYSCTL1_SYSCFG_SDR_PAD_DRV_2 2 +#endif + +#define SYSCTL_SYSCFG1 0x14 +#define SYSCTL_SYSCFG1_USB0_HOST_MODE (1 << 10) #define SYSCTL_TESTSTAT 0x18 #define SYSCTL_TESTSTAT2 0x1C @@ -142,7 +254,10 @@ #define SYSCTL_CLKCFG0_SDRAM_CLK_SKEW_3NS_DELAY 3 #define SYSCTL_CLKCFG1 0x30 +#if !defined(RT5350) #define SYSCTL_CLKCFG1_PBUS_DIV_CLK_BY2 (1<<30) +#define SYSCTL_CLKCFG1_UPHY0_CLK_EN (1<<25) +#define SYSCTL_CLKCFG1_UPHY1_CLK_EN (1<<22) #define SYSCTL_CLKCFG1_OTG_CLK_EN (1<<18) #define SYSCTL_CLKCFG1_I2S_CLK_EN (1<<15) #define SYSCTL_CLKCFG1_I2S_CLK_SEL_EXT (1<<14) @@ -152,10 +267,21 @@ #define SYSCTL_CLKCFG1_PCM_CLK_SEL_EXT (1<<6) #define SYSCTL_CLKCFG1_PCM_CLK_DIV_MASK 0x0000003f #define SYSCTL_CLKCFG1_PCM_CLK_DIV_SHIFT 0 +#endif +#ifdef RT5350 +#define SYSCTL_CLKCFG1_SYSTICK_EN (1<<29) +#define SYSCTL_CLKCFG1_PDMA_CSR_CLK_GATE_BYP (1<<23) +#define SYSCTL_CLKCFG1_UPHY0_CLK_EN (1<<18) +#endif #define SYSCTL_RSTCTRL 0x34 #define SYSCTL_RSTCTRL_ETHSW (1<<23) +#if !defined(MT7620) && !defined(RT5350) #define SYSCTL_RSTCTRL_OTG (1<<22) +#else +#define SYSCTL_RSTCTRL_UPHY0 (1<<25) +#define SYSCTL_RSTCTRL_UPHY1 (1<<22) +#endif #define SYSCTL_RSTCTRL_FRENG (1<<21) #define SYSCTL_RSTCTRL_WLAN (1<<20) #define SYSCTL_RSTCTRL_UARTL (1<<19) @@ -196,6 +322,9 @@ #define SYSCTL_MEMO0 0x68 #define SYSCTL_MEMO1 0x6C +#define SYSCTL_PPLL_CFG1 0x9C +#define SYSCTL_PPLL_DRV 0xA0 + /* Timer */ #define TIMER_TMRSTAT 0x00 #define TIMER_TMRSTAT_TMR1RST (1<<5) @@ -249,7 +378,10 @@ #define IC_OTG 18 #define IC_ETHSW 17 +#define IC_R2P 15 +#define IC_SDHC 14 #define IC_UARTLITE 12 +#define IC_SPI 11 #define IC_I2S 10 #define IC_PERFC 9 #define IC_NAND 8 @@ -362,7 +494,39 @@ */ #define GDMACT0_SWMODE (1<<0) +/* SPI controller interface */ + +#define RT305X_SPISTAT 0x00 +/* SPIBUSY is alias for SPIBUSY, because SPISTAT have only BUSY bit*/ +#define RT305X_SPIBUSY RT305X_SPISTAT + +#define RT305X_SPICFG 0x10 +#define MSBFIRST (1<<8) +#define SPICLKPOL (1<<6) +#define CAPT_ON_CLK_FALL (1<<5) +#define TX_ON_CLK_FALL (1<<4) +#define HIZSPI (1<<3) /* Set SPI pins to Tri-state */ +#define SPI_CLK_SHIFT 0 /* SPI clock divide control */ +#define SPI_CLK_MASK 0x00000007 +#define SPI_CLK_DIV2 0 +#define SPI_CLK_DIV4 1 +#define SPI_CLK_DIV8 2 +#define SPI_CLK_DIV16 3 +#define SPI_CLK_DIV32 4 +#define SPI_CLK_DIV64 5 +#define SPI_CLK_DIV128 6 +#define SPI_CLK_DISABLED 7 + +#define RT305X_SPICTL 0x14 +#define HIZSMOSI (1<<3) +#define START_WRITE (1<<2) +#define START_READ (1<<1) +#define CS_HIGH (1<<0) +#define RT305X_SPIDATA 0x20 +#define SPIDATA_MASK 0x000000ff +#define RT305X_SPI_WRITE 1 +#define RT305X_SPI_READ 0 #endif /* _RT305XREG_H_ */ _______________________________________________ svn-src-head@freebsd.org mailing list https://lists.freebsd.org/mailman/listinfo/svn-src-head To unsubscribe, send any mail to "svn-src-head-unsubscr...@freebsd.org"
