Author: mmel
Date: Sun Jan 31 08:53:53 2016
New Revision: 295090
URL: https://svnweb.freebsd.org/changeset/base/295090
Log:
ARM: Convert spaces to tabs, fix formatting.
Not a functional change.
Modified:
head/sys/arm/arm/swtch-v4.S
head/sys/arm/arm/swtch-v6.S
Modified: head/sys/arm/arm/swtch-v4.S
==============================================================================
--- head/sys/arm/arm/swtch-v4.S Sun Jan 31 08:06:22 2016 (r295089)
+++ head/sys/arm/arm/swtch-v4.S Sun Jan 31 08:53:53 2016 (r295090)
@@ -98,7 +98,7 @@ __FBSDID("$FreeBSD$");
#endif
.Lcurpcpu:
- .word _C_LABEL(__pcpu)
+ .word _C_LABEL(__pcpu)
.Lblocked_lock:
.word _C_LABEL(blocked_lock)
@@ -129,7 +129,7 @@ ENTRY(cpu_throw)
#endif
GET_PCPU(r7, r9)
- ldr r7, [r5, #(TD_PCB)] /* r7 = new thread's PCB */
+ ldr r7, [r5, #(TD_PCB)] /* r7 = new thread's PCB */
/* Switch to lwp0 context */
@@ -275,25 +275,25 @@ ENTRY(cpu_switch)
/* rem: r2 = old PCB */
/* rem: r9 = new PCB */
- ldr r5, [r9, #(PCB_DACR)] /* r5 = new DACR */
+ ldr r5, [r9, #(PCB_DACR)] /* r5 = new DACR */
mov r2, #DOMAIN_CLIENT
- cmp r5, r2, lsl #(PMAP_DOMAIN_KERNEL * 2) /* Sw to kernel thread? */
- beq .Lcs_context_switched /* Yup. Don't flush cache */
- mrc p15, 0, r0, c3, c0, 0 /* r0 = old DACR */
+ cmp r5, r2, lsl #(PMAP_DOMAIN_KERNEL * 2) /* Sw to kernel thread? */
+ beq .Lcs_context_switched /* Yup. Don't flush cache */
+ mrc p15, 0, r0, c3, c0, 0 /* r0 = old DACR */
/*
- * Get the new L1 table pointer into r11. If we're switching to
+ * Get the new L1 table pointer into r11. If we're switching to
* an LWP with the same address space as the outgoing one, we can
* skip the cache purge and the TTB load.
*
* To avoid data dep stalls that would happen anyway, we try
* and get some useful work done in the mean time.
*/
- mrc p15, 0, r10, c2, c0, 0 /* r10 = old L1 */
- ldr r11, [r9, #(PCB_PAGEDIR)] /* r11 = new L1 */
+ mrc p15, 0, r10, c2, c0, 0 /* r10 = old L1 */
+ ldr r11, [r9, #(PCB_PAGEDIR)] /* r11 = new L1 */
- teq r10, r11 /* Same L1? */
- cmpeq r0, r5 /* Same DACR? */
- beq .Lcs_context_switched /* yes! */
+ teq r10, r11 /* Same L1? */
+ cmpeq r0, r5 /* Same DACR? */
+ beq .Lcs_context_switched /* yes! */
/*
* Definately need to flush the cache.
@@ -375,6 +375,3 @@ ENTRY(cpu_switch)
add r3, r9, #PCB_R4
ldmia r3, {r4-r12, sp, pc}
END(cpu_switch)
-
-
-
Modified: head/sys/arm/arm/swtch-v6.S
==============================================================================
--- head/sys/arm/arm/swtch-v6.S Sun Jan 31 08:06:22 2016 (r295089)
+++ head/sys/arm/arm/swtch-v6.S Sun Jan 31 08:53:53 2016 (r295090)
@@ -109,7 +109,7 @@ __FBSDID("$FreeBSD$");
#endif
.Lcurpcpu:
- .word _C_LABEL(__pcpu)
+ .word _C_LABEL(__pcpu)
.word PCPU_SIZE
.Lblocked_lock:
.word _C_LABEL(blocked_lock)
@@ -134,7 +134,7 @@ ENTRY(cpu_context_switch) /* QQQ: What a
* it's the only place where standalone predictor flush must be
* executed in kernel (except self modifying code case).
*/
- mcr CP15_BPIALL /* and flush entire Branch Target Cache */
+ mcr CP15_BPIALL /* flush entire Branch Target Cache */
DSB
mov pc, lr
END(cpu_context_switch)
@@ -155,9 +155,9 @@ ENTRY(cpu_throw)
bl _C_LABEL(vfp_discard) /* VFP without preserving state. */
#endif
GET_PCPU(r8, r9) /* r8 = current pcpu */
- ldr r4, [r8, #PC_CPUID] /* r4 = current cpu id */
+ ldr r4, [r8, #PC_CPUID] /* r4 = current cpu id */
- cmp r10, #0 /* old thread? */
+ cmp r10, #0 /* old thread? */
beq 2f /* no, skip */
/* Remove this CPU from the active list. */
@@ -206,7 +206,7 @@ ENTRY(cpu_throw)
*/
/* MMU switch to new thread. */
- ldr r0, [r7, #(PCB_PAGEDIR)]
+ ldr r0, [r7, #(PCB_PAGEDIR)]
#ifdef INVARIANTS
cmp r0, #0 /* new thread? */
beq badsw4 /* no, panic */
@@ -290,11 +290,11 @@ ENTRY(cpu_switch)
* it is time to restore them for the new thread. However,
* some registers are not safe over function call.
*/
- mov r9, r2 /* r9 = lock */
+ mov r9, r2 /* r9 = lock */
mov r10, r0 /* r10 = oldtd */
mov r11, r1 /* r11 = newtd */
- GET_PCPU(r8, r3) /* r8 = current PCPU */
+ GET_PCPU(r8, r3) /* r8 = current PCPU */
ldr r7, [r11, #(TD_PCB)] /* r7 = newtd->td_pcb */
@@ -341,8 +341,8 @@ ENTRY(cpu_switch)
ldr r6, [r6, #P_VMSPACE] /* newtd->proc->vmspace */
add r6, #VM_PMAP /* newtd->proc->vmspace->pmap */
- ldr r5, [r8, #PC_CURPMAP] /* get old curpmap */
- str r6, [r8, #PC_CURPMAP] /* and save new one */
+ ldr r5, [r8, #PC_CURPMAP] /* get old curpmap */
+ str r6, [r8, #PC_CURPMAP] /* and save new one */
mov r0, #PM_ACTIVE
add r5, r0 /* r5 = old pm_active */
@@ -376,7 +376,7 @@ ENTRY(cpu_switch)
#endif
/* Set cpu to new active list. */
#ifdef SMP
-1: ldrex r0, [r6]
+1: ldrex r0, [r6]
orr r0, r2
strex r1, r0, [r6]
teq r1, #0
@@ -427,7 +427,7 @@ sw1:
beq 1b
#endif
/* Set the new tls */
- ldr r0, [r11, #(TD_MD + MD_TP)]
+ ldr r0, [r11, #(TD_MD + MD_TP)]
mcr CP15_TPIDRURO(r0) /* write tls thread reg 2 */
/* We have a new curthread now so make a note it */
@@ -450,7 +450,7 @@ badsw1:
ldr r0, =sw1_panic_str
bl _C_LABEL(panic)
1: nop
- b 1b
+ b 1b
badsw2:
ldr r0, =sw2_panic_str
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