Author: mmel
Date: Fri Feb 5 14:57:41 2016
New Revision: 295319
URL: https://svnweb.freebsd.org/changeset/base/295319
Log:
ARM: Use new ARMv6 naming conventions for cache and TLB functions
in all but ARMv4 specific files.
Expand ARMv6 compatibility stubs in cpu-v4.h. Use physical address
in L2 cache functions if ARM_L2_PIPT is defined.
Modified:
head/sys/arm/allwinner/a20/a20_mp.c
head/sys/arm/altera/socfpga/socfpga_mp.c
head/sys/arm/amlogic/aml8726/aml8726_mp.c
head/sys/arm/arm/db_interface.c
head/sys/arm/arm/dump_machdep.c
head/sys/arm/arm/fiq.c
head/sys/arm/arm/machdep.c
head/sys/arm/arm/minidump_machdep.c
head/sys/arm/arm/mp_machdep.c
head/sys/arm/arm/sys_machdep.c
head/sys/arm/broadcom/bcm2835/bcm2836_mp.c
head/sys/arm/freescale/imx/imx6_mp.c
head/sys/arm/include/cpu-v4.h
head/sys/arm/include/cpu-v6.h
head/sys/arm/include/cpufunc.h
head/sys/arm/include/kdb.h
head/sys/arm/mv/armada38x/pmsu.c
head/sys/arm/mv/armadaxp/armadaxp_mp.c
head/sys/arm/rockchip/rk30xx_mp.c
head/sys/arm/samsung/exynos/exynos5_mp.c
head/sys/arm/ti/omap4/omap4_mp.c
head/sys/arm/xilinx/zy7_mp.c
head/sys/contrib/vchiq/interface/vchiq_arm/vchiq_2835_arm.c
Modified: head/sys/arm/allwinner/a20/a20_mp.c
==============================================================================
--- head/sys/arm/allwinner/a20/a20_mp.c Fri Feb 5 14:16:42 2016
(r295318)
+++ head/sys/arm/allwinner/a20/a20_mp.c Fri Feb 5 14:57:41 2016
(r295319)
@@ -37,6 +37,7 @@ __FBSDID("$FreeBSD$");
#include <vm/vm.h>
#include <vm/pmap.h>
+#include <machine/cpu.h>
#include <machine/smp.h>
#include <machine/fdt.h>
#include <machine/intr.h>
@@ -101,8 +102,7 @@ platform_mp_start_ap(void)
&cpucfg) != 0)
panic("Couldn't map the CPUCFG\n");
- cpu_idcache_wbinv_all();
- cpu_l2cache_wbinv_all();
+ dcache_wbinv_poc_all();
bus_space_write_4(fdtbus_bs_tag, cpucfg, CPUCFG_P_REG0,
pmap_kextract((vm_offset_t)mpentry));
Modified: head/sys/arm/altera/socfpga/socfpga_mp.c
==============================================================================
--- head/sys/arm/altera/socfpga/socfpga_mp.c Fri Feb 5 14:16:42 2016
(r295318)
+++ head/sys/arm/altera/socfpga/socfpga_mp.c Fri Feb 5 14:57:41 2016
(r295319)
@@ -41,6 +41,7 @@ __FBSDID("$FreeBSD$");
#include <vm/vm.h>
#include <vm/pmap.h>
+#include <machine/cpu.h>
#include <machine/smp.h>
#include <machine/fdt.h>
#include <machine/intr.h>
@@ -162,8 +163,7 @@ platform_mp_start_ap(void)
bus_space_write_region_4(fdtbus_bs_tag, ram, 0,
(uint32_t *)&socfpga_trampoline, 8);
- cpu_idcache_wbinv_all();
- cpu_l2cache_wbinv_all();
+ dcache_wbinv_poc_all();
/* Put CPU1 out from reset */
bus_space_write_4(fdtbus_bs_tag, rst, MPUMODRST, 0);
Modified: head/sys/arm/amlogic/aml8726/aml8726_mp.c
==============================================================================
--- head/sys/arm/amlogic/aml8726/aml8726_mp.c Fri Feb 5 14:16:42 2016
(r295318)
+++ head/sys/arm/amlogic/aml8726/aml8726_mp.c Fri Feb 5 14:57:41 2016
(r295319)
@@ -53,6 +53,7 @@ __FBSDID("$FreeBSD$");
#include <vm/vm.h>
#include <vm/pmap.h>
+#include <machine/cpu.h>
#include <machine/bus.h>
#include <machine/smp.h>
#include <machine/fdt.h>
@@ -485,7 +486,7 @@ platform_mp_start_ap(void)
value |= AML_SCU_CONTROL_ENABLE;
SCU_WRITE_4(AML_SCU_CONTROL_REG, value);
SCU_BARRIER(AML_SCU_CONTROL_REG);
- cpu_idcache_wbinv_all();
+ dcache_wbinv_poc_all();
/* Set the boot address and power on each AP. */
paddr = pmap_kextract((vm_offset_t)mpentry);
Modified: head/sys/arm/arm/db_interface.c
==============================================================================
--- head/sys/arm/arm/db_interface.c Fri Feb 5 14:16:42 2016
(r295318)
+++ head/sys/arm/arm/db_interface.c Fri Feb 5 14:57:41 2016
(r295319)
@@ -39,6 +39,7 @@ __FBSDID("$FreeBSD$");
#include "opt_ddb.h"
#include <sys/param.h>
+#include <sys/cons.h>
#include <sys/proc.h>
#include <sys/reboot.h>
#include <sys/systm.h> /* just for boothowto */
@@ -53,9 +54,9 @@ __FBSDID("$FreeBSD$");
#include <vm/vm_extern.h>
#include <machine/db_machdep.h>
+#include <machine/cpu.h>
#include <machine/machdep.h>
#include <machine/vmparam.h>
-#include <machine/cpu.h>
#include <ddb/ddb.h>
#include <ddb/db_access.h>
@@ -63,7 +64,7 @@ __FBSDID("$FreeBSD$");
#include <ddb/db_output.h>
#include <ddb/db_variables.h>
#include <ddb/db_sym.h>
-#include <sys/cons.h>
+
static int nil = 0;
@@ -245,11 +246,10 @@ db_write_bytes(vm_offset_t addr, size_t
}
/* make sure the caches and memory are in sync */
- cpu_icache_sync_range(addr, size);
+ icache_sync(addr, size);
/* In case the current page tables have been modified ... */
- cpu_tlb_flushID();
- cpu_cpwait();
+ tlb_flush_all();
return (0);
}
Modified: head/sys/arm/arm/dump_machdep.c
==============================================================================
--- head/sys/arm/arm/dump_machdep.c Fri Feb 5 14:16:42 2016
(r295318)
+++ head/sys/arm/arm/dump_machdep.c Fri Feb 5 14:57:41 2016
(r295319)
@@ -59,8 +59,7 @@ dumpsys_wbinv_all(void)
* have already been stopped, and their flush/invalidate was done as
* part of stopping.
*/
- cpu_idcache_wbinv_all();
- cpu_l2cache_wbinv_all();
+ dcache_wbinv_poc_all();
#ifdef __XSCALE__
xscale_cache_clean_minidata();
#endif
Modified: head/sys/arm/arm/fiq.c
==============================================================================
--- head/sys/arm/arm/fiq.c Fri Feb 5 14:16:42 2016 (r295318)
+++ head/sys/arm/arm/fiq.c Fri Feb 5 14:57:41 2016 (r295319)
@@ -81,8 +81,8 @@ fiq_installhandler(void *func, size_t si
#if !defined(__ARM_FIQ_INDIRECT)
vector_page_setprot(VM_PROT_READ);
- cpu_icache_sync_range((vm_offset_t) fiqvector, size);
#endif
+ icache_sync((vm_offset_t) fiqvector, size);
}
/*
Modified: head/sys/arm/arm/machdep.c
==============================================================================
--- head/sys/arm/arm/machdep.c Fri Feb 5 14:16:42 2016 (r295318)
+++ head/sys/arm/arm/machdep.c Fri Feb 5 14:57:41 2016 (r295319)
@@ -396,7 +396,7 @@ arm_vector_init(vm_offset_t va, int whic
}
/* Now sync the vectors. */
- cpu_icache_sync_range(va, (ARM_NVEC * 2) * sizeof(u_int));
+ icache_sync(va, (ARM_NVEC * 2) * sizeof(u_int));
vector_page = va;
@@ -478,12 +478,7 @@ void
cpu_flush_dcache(void *ptr, size_t len)
{
- cpu_dcache_wb_range((uintptr_t)ptr, len);
-#ifdef ARM_L2_PIPT
- cpu_l2cache_wb_range((uintptr_t)vtophys(ptr), len);
-#else
- cpu_l2cache_wb_range((uintptr_t)ptr, len);
-#endif
+ dcache_wb_poc((vm_offset_t)ptr, (vm_paddr_t)vtophys(ptr), len);
}
/* Get current clock frequency for the given cpu id. */
Modified: head/sys/arm/arm/minidump_machdep.c
==============================================================================
--- head/sys/arm/arm/minidump_machdep.c Fri Feb 5 14:16:42 2016
(r295318)
+++ head/sys/arm/arm/minidump_machdep.c Fri Feb 5 14:57:41 2016
(r295319)
@@ -45,11 +45,11 @@ __FBSDID("$FreeBSD$");
#include <vm/vm.h>
#include <vm/pmap.h>
#include <machine/atomic.h>
+#include <machine/cpu.h>
#include <machine/elf.h>
#include <machine/md_var.h>
-#include <machine/vmparam.h>
#include <machine/minidump.h>
-#include <machine/cpufunc.h>
+#include <machine/vmparam.h>
CTASSERT(sizeof(struct kerneldumpheader) == 512);
@@ -203,8 +203,7 @@ minidumpsys(struct dumperinfo *di)
* by time we get to here, all that remains is to flush the L1 for the
* current CPU, then the L2.
*/
- cpu_idcache_wbinv_all();
- cpu_l2cache_wbinv_all();
+ dcache_wbinv_poc_all();
counter = 0;
/* Walk page table pages, set bits in vm_page_dump */
Modified: head/sys/arm/arm/mp_machdep.c
==============================================================================
--- head/sys/arm/arm/mp_machdep.c Fri Feb 5 14:16:42 2016
(r295318)
+++ head/sys/arm/arm/mp_machdep.c Fri Feb 5 14:57:41 2016
(r295319)
@@ -123,9 +123,7 @@ cpu_mp_start(void)
dpcpu[i] = (void *)kmem_malloc(kernel_arena, DPCPU_SIZE,
M_WAITOK | M_ZERO);
- cpu_idcache_wbinv_all();
- cpu_l2cache_wbinv_all();
- cpu_idcache_wbinv_all();
+ dcache_wbinv_poc_all();
/* Initialize boot code and start up processors */
platform_mp_start_ap();
@@ -283,7 +281,7 @@ ipi_stop(void *dummy __unused)
* stop will do the l2 cache flush after all other cores
* have done their l1 flushes and stopped.
*/
- cpu_idcache_wbinv_all();
+ dcache_wbinv_poc_all();
/* Indicate we are stopped */
CPU_SET_ATOMIC(cpu, &stopped_cpus);
@@ -381,7 +379,7 @@ ipi_handler(void *arg)
* stop will do the l2 cache flush after all other cores
* have done their l1 flushes and stopped.
*/
- cpu_idcache_wbinv_all();
+ dcache_wbinv_poc_all();
/* Indicate we are stopped */
CPU_SET_ATOMIC(cpu, &stopped_cpus);
Modified: head/sys/arm/arm/sys_machdep.c
==============================================================================
--- head/sys/arm/arm/sys_machdep.c Fri Feb 5 14:16:42 2016
(r295318)
+++ head/sys/arm/arm/sys_machdep.c Fri Feb 5 14:57:41 2016
(r295319)
@@ -153,8 +153,13 @@ arm32_drain_writebuf(struct thread *td,
{
/* No args. */
- td->td_retval[0] = 0;
+#if __ARM_ARCH < 6
cpu_drain_writebuf();
+#else
+ dsb();
+ cpu_l2cache_drain_writebuf();
+#endif
+ td->td_retval[0] = 0;
return (0);
}
Modified: head/sys/arm/broadcom/bcm2835/bcm2836_mp.c
==============================================================================
--- head/sys/arm/broadcom/bcm2835/bcm2836_mp.c Fri Feb 5 14:16:42 2016
(r295318)
+++ head/sys/arm/broadcom/bcm2835/bcm2836_mp.c Fri Feb 5 14:57:41 2016
(r295319)
@@ -40,6 +40,7 @@ __FBSDID("$FreeBSD$");
#include <vm/vm.h>
#include <vm/pmap.h>
+#include <machine/cpu.h>
#include <machine/smp.h>
#include <machine/bus.h>
#include <machine/fdt.h>
@@ -123,8 +124,7 @@ platform_mp_start_ap(void)
BSWR4(MBOX3CLR_CORE(i), 0xffffffff);
}
wmb();
- cpu_idcache_wbinv_all();
- cpu_l2cache_wbinv_all();
+ dcache_wbinv_poc_all();
/* boot secondary CPUs */
for (i = 1; i < mp_ncpus; i++) {
Modified: head/sys/arm/freescale/imx/imx6_mp.c
==============================================================================
--- head/sys/arm/freescale/imx/imx6_mp.c Fri Feb 5 14:16:42 2016
(r295318)
+++ head/sys/arm/freescale/imx/imx6_mp.c Fri Feb 5 14:57:41 2016
(r295319)
@@ -37,6 +37,7 @@ __FBSDID("$FreeBSD$");
#include <vm/vm.h>
#include <vm/pmap.h>
+#include <machine/cpu.h>
#include <machine/smp.h>
#include <machine/fdt.h>
#include <machine/intr.h>
@@ -149,7 +150,7 @@ platform_mp_start_ap(void)
val = bus_space_read_4(fdtbus_bs_tag, scu, SCU_CONTROL_REG);
bus_space_write_4(fdtbus_bs_tag, scu, SCU_CONTROL_REG,
val | SCU_CONTROL_ENABLE);
- cpu_idcache_wbinv_all();
+ dcache_wbinv_poc_all();
/*
* For each AP core, set the entry point address and argument registers,
Modified: head/sys/arm/include/cpu-v4.h
==============================================================================
--- head/sys/arm/include/cpu-v4.h Fri Feb 5 14:16:42 2016
(r295318)
+++ head/sys/arm/include/cpu-v4.h Fri Feb 5 14:57:41 2016
(r295319)
@@ -41,7 +41,7 @@
#include <machine/sysreg.h>
#if __ARM_ARCH >= 6
-#error Newer include this file for ARMv6
+#error Never include this file for ARMv6
#else
#define CPU_ASID_KERNEL 0
@@ -125,11 +125,28 @@ _RF0(cp15_tlbtr_get, CP15_TLBTR(%0))
*/
static __inline void
+tlb_flush_all(void)
+{
+ cpu_tlb_flushID();
+ cpu_cpwait();
+}
+
+static __inline void
+icache_sync(vm_offset_t va, vm_size_t size)
+{
+ cpu_icache_sync_range(va, size);
+}
+
+static __inline void
dcache_inv_poc(vm_offset_t va, vm_paddr_t pa, vm_size_t size)
{
cpu_dcache_inv_range(va, size);
+#ifdef ARM_L2_PIPT
+ cpu_l2cache_inv_range(pa, size);
+#else
cpu_l2cache_inv_range(va, size);
+#endif
}
static __inline void
@@ -137,7 +154,11 @@ dcache_inv_poc_dma(vm_offset_t va, vm_pa
{
/* See armv6 code, above, for why we do L2 before L1 in this case. */
+#ifdef ARM_L2_PIPT
+ cpu_l2cache_inv_range(pa, size);
+#else
cpu_l2cache_inv_range(va, size);
+#endif
cpu_dcache_inv_range(va, size);
}
@@ -146,7 +167,18 @@ dcache_wb_poc(vm_offset_t va, vm_paddr_t
{
cpu_dcache_wb_range(va, size);
+#ifdef ARM_L2_PIPT
+ cpu_l2cache_wb_range(pa, size);
+#else
cpu_l2cache_wb_range(va, size);
+#endif
+}
+
+static __inline void
+dcache_wbinv_poc_all(void)
+{
+ cpu_idcache_wbinv_all();
+ cpu_l2cache_wbinv_all();
}
#endif /* _KERNEL */
Modified: head/sys/arm/include/cpu-v6.h
==============================================================================
--- head/sys/arm/include/cpu-v6.h Fri Feb 5 14:16:42 2016
(r295318)
+++ head/sys/arm/include/cpu-v6.h Fri Feb 5 14:57:41 2016
(r295319)
@@ -44,10 +44,9 @@
#error Only include this file for ARMv6
#else
-
-
#define CPU_ASID_KERNEL 0
+void dcache_wbinv_poc_all(void); /* !!! NOT SMP coherent function !!! */
vm_offset_t dcache_wb_pou_checked(vm_offset_t, vm_size_t);
vm_offset_t icache_inv_pou_checked(vm_offset_t, vm_size_t);
Modified: head/sys/arm/include/cpufunc.h
==============================================================================
--- head/sys/arm/include/cpufunc.h Fri Feb 5 14:16:42 2016
(r295318)
+++ head/sys/arm/include/cpufunc.h Fri Feb 5 14:57:41 2016
(r295319)
@@ -161,9 +161,12 @@ struct cpu_functions {
extern struct cpu_functions cpufuncs;
extern u_int cputype;
+#if __ARM_ARCH < 6
#define cpu_cpwait() cpufuncs.cf_cpwait()
+#endif
#define cpu_control(c, e) cpufuncs.cf_control(c, e)
+#if __ARM_ARCH < 6
#define cpu_setttb(t) cpufuncs.cf_setttb(t)
#define cpu_tlb_flushID() cpufuncs.cf_tlb_flushID()
@@ -181,13 +184,16 @@ extern u_int cputype;
#define cpu_idcache_inv_all() cpufuncs.cf_idcache_inv_all()
#define cpu_idcache_wbinv_all() cpufuncs.cf_idcache_wbinv_all()
#define cpu_idcache_wbinv_range(a, s)
cpufuncs.cf_idcache_wbinv_range((a), (s))
+#endif
#define cpu_l2cache_wbinv_all() cpufuncs.cf_l2cache_wbinv_all()
#define cpu_l2cache_wb_range(a, s) cpufuncs.cf_l2cache_wb_range((a), (s))
#define cpu_l2cache_inv_range(a, s) cpufuncs.cf_l2cache_inv_range((a), (s))
#define cpu_l2cache_wbinv_range(a, s) cpufuncs.cf_l2cache_wbinv_range((a), (s))
#define cpu_l2cache_drain_writebuf() cpufuncs.cf_l2cache_drain_writebuf()
+#if __ARM_ARCH < 6
#define cpu_drain_writebuf() cpufuncs.cf_drain_writebuf()
+#endif
#define cpu_sleep(m) cpufuncs.cf_sleep(m)
#define cpu_setup() cpufuncs.cf_setup()
Modified: head/sys/arm/include/kdb.h
==============================================================================
--- head/sys/arm/include/kdb.h Fri Feb 5 14:16:42 2016 (r295318)
+++ head/sys/arm/include/kdb.h Fri Feb 5 14:57:41 2016 (r295319)
@@ -29,10 +29,10 @@
#ifndef _MACHINE_KDB_H_
#define _MACHINE_KDB_H_
+#include <machine/cpu.h>
+#include <machine/db_machdep.h>
#include <machine/frame.h>
#include <machine/psl.h>
-#include <machine/cpufunc.h>
-#include <machine/db_machdep.h>
#define KDB_STOPPEDPCB(pc) &stoppcbs[pc->pc_cpuid]
@@ -56,7 +56,7 @@ static __inline void
kdb_cpu_sync_icache(unsigned char *addr, size_t size)
{
- cpu_icache_sync_range((vm_offset_t)addr, size);
+ icache_sync((vm_offset_t)addr, size);
}
static __inline void
Modified: head/sys/arm/mv/armada38x/pmsu.c
==============================================================================
--- head/sys/arm/mv/armada38x/pmsu.c Fri Feb 5 14:16:42 2016
(r295318)
+++ head/sys/arm/mv/armada38x/pmsu.c Fri Feb 5 14:57:41 2016
(r295319)
@@ -36,10 +36,12 @@ __FBSDID("$FreeBSD$");
#include <sys/kernel.h>
#include <sys/module.h>
#include <sys/resource.h>
+#include <sys/systm.h>
#include <vm/vm.h>
#include <vm/pmap.h>
+#include <machine/cpu.h>
#include <machine/fdt.h>
#include <machine/smp.h>
@@ -143,8 +145,7 @@ pmsu_boot_secondary_cpu(void)
bus_space_write_4(fdtbus_bs_tag, vaddr,
PMSU_BOOT_ADDR_REDIRECT_OFFSET(1),
pmap_kextract((vm_offset_t)mpentry));
- cpu_idcache_wbinv_all();
- cpu_l2cache_wbinv_all();
+ dcache_wbinv_poc_all();
armv7_sev();
bus_space_unmap(fdtbus_bs_tag, vaddr, MV_PMSU_REGS_LEN);
Modified: head/sys/arm/mv/armadaxp/armadaxp_mp.c
==============================================================================
--- head/sys/arm/mv/armadaxp/armadaxp_mp.c Fri Feb 5 14:16:42 2016
(r295318)
+++ head/sys/arm/mv/armadaxp/armadaxp_mp.c Fri Feb 5 14:57:41 2016
(r295319)
@@ -40,6 +40,7 @@
#include <dev/fdt/fdt_common.h>
+#include <machine/cpu.h>
#include <machine/smp.h>
#include <machine/fdt.h>
#include <machine/armreg.h>
@@ -174,7 +175,7 @@ platform_mp_start_ap(void)
bus_space_write_4(fdtbus_bs_tag, CPU_PMU(cpu_num), CPU_PMU_BOOT,
pmap_kextract((vm_offset_t)mpentry));
- cpu_idcache_wbinv_all();
+ dcache_wbinv_poc_all();
for (cpu_num = 1; cpu_num < mp_ncpus; cpu_num++ )
bus_space_write_4(fdtbus_bs_tag, MP, MP_SW_RESET(cpu_num), 0);
Modified: head/sys/arm/rockchip/rk30xx_mp.c
==============================================================================
--- head/sys/arm/rockchip/rk30xx_mp.c Fri Feb 5 14:16:42 2016
(r295318)
+++ head/sys/arm/rockchip/rk30xx_mp.c Fri Feb 5 14:57:41 2016
(r295319)
@@ -36,6 +36,7 @@ __FBSDID("$FreeBSD$");
#include <vm/vm.h>
#include <vm/pmap.h>
+#include <machine/cpu.h>
#include <machine/smp.h>
#include <machine/fdt.h>
#include <machine/intr.h>
@@ -171,8 +172,7 @@ platform_mp_start_ap(void)
bus_space_write_region_4(fdtbus_bs_tag, imem, 0,
(uint32_t *)&rk30xx_boot2, 8);
- cpu_idcache_wbinv_all();
- cpu_l2cache_wbinv_all();
+ dcache_wbinv_poc_all();
/* Start all cores */
val = bus_space_read_4(fdtbus_bs_tag, pmu, PMU_PWRDN_CON);
Modified: head/sys/arm/samsung/exynos/exynos5_mp.c
==============================================================================
--- head/sys/arm/samsung/exynos/exynos5_mp.c Fri Feb 5 14:16:42 2016
(r295318)
+++ head/sys/arm/samsung/exynos/exynos5_mp.c Fri Feb 5 14:57:41 2016
(r295319)
@@ -36,6 +36,7 @@ __FBSDID("$FreeBSD$");
#include <vm/vm.h>
#include <vm/pmap.h>
+#include <machine/cpu.h>
#include <machine/smp.h>
#include <machine/fdt.h>
#include <machine/intr.h>
@@ -135,8 +136,7 @@ platform_mp_start_ap(void)
bus_space_write_4(fdtbus_bs_tag, sysram, 0x0,
pmap_kextract((vm_offset_t)mpentry));
- cpu_idcache_wbinv_all();
- cpu_l2cache_wbinv_all();
+ dcache_wbinv_poc_all();
armv7_sev();
bus_space_unmap(fdtbus_bs_tag, sysram, 0x100);
Modified: head/sys/arm/ti/omap4/omap4_mp.c
==============================================================================
--- head/sys/arm/ti/omap4/omap4_mp.c Fri Feb 5 14:16:42 2016
(r295318)
+++ head/sys/arm/ti/omap4/omap4_mp.c Fri Feb 5 14:57:41 2016
(r295319)
@@ -34,6 +34,7 @@ __FBSDID("$FreeBSD$");
#include <vm/vm.h>
#include <vm/pmap.h>
+#include <machine/cpu.h>
#include <machine/smp.h>
#include <machine/fdt.h>
#include <machine/intr.h>
@@ -72,8 +73,8 @@ platform_mp_start_ap(void)
/* Enable the SCU */
*(volatile unsigned int *)scu_addr |= 1;
//*(volatile unsigned int *)(scu_addr + 0x30) |= 1;
- cpu_idcache_wbinv_all();
- cpu_l2cache_wbinv_all();
+ dcache_wbinv_poc_all();
+
ti_smc0(0x200, 0xfffffdff, MODIFY_AUX_CORE_0);
ti_smc0(pmap_kextract((vm_offset_t)mpentry), 0, WRITE_AUX_CORE_1);
armv7_sev();
Modified: head/sys/arm/xilinx/zy7_mp.c
==============================================================================
--- head/sys/arm/xilinx/zy7_mp.c Fri Feb 5 14:16:42 2016
(r295318)
+++ head/sys/arm/xilinx/zy7_mp.c Fri Feb 5 14:57:41 2016
(r295319)
@@ -34,6 +34,7 @@ __FBSDID("$FreeBSD$");
#include <vm/vm.h>
#include <vm/pmap.h>
+#include <machine/cpu.h>
#include <machine/smp.h>
#include <machine/fdt.h>
#include <machine/intr.h>
@@ -104,8 +105,7 @@ platform_mp_start_ap(void)
* magic location, 0xfffffff0, isn't in the SCU's filtering range so it
* needs a write-back too.
*/
- cpu_idcache_wbinv_all();
- cpu_l2cache_wbinv_all();
+ dcache_wbinv_poc_all();
/* Wake up CPU1. */
armv7_sev();
Modified: head/sys/contrib/vchiq/interface/vchiq_arm/vchiq_2835_arm.c
==============================================================================
--- head/sys/contrib/vchiq/interface/vchiq_arm/vchiq_2835_arm.c Fri Feb 5
14:16:42 2016 (r295318)
+++ head/sys/contrib/vchiq/interface/vchiq_arm/vchiq_2835_arm.c Fri Feb 5
14:57:41 2016 (r295319)
@@ -48,6 +48,7 @@
#include <vm/vm_phys.h>
#include <machine/bus.h>
+#include <machine/cpu.h>
#include <arm/broadcom/bcm2835/bcm2835_mbox.h>
#include <arm/broadcom/bcm2835/bcm2835_vcbus.h>
@@ -411,6 +412,7 @@ create_pagelist(char __user *buf, size_t
int run, addridx, actual_pages;
int err;
vm_paddr_t pagelist_phys;
+ vm_paddr_t pa;
offset = (vm_offset_t)buf & (PAGE_SIZE - 1);
num_pages = (count + offset + PAGE_SIZE - 1) / PAGE_SIZE;
@@ -533,7 +535,8 @@ create_pagelist(char __user *buf, size_t
(fragments - g_fragments_base)/g_fragment_size;
}
- cpu_dcache_wbinv_range((vm_offset_t)buf, count);
+ pa = pmap_extract(PCPU_GET(curpmap), (vm_offset_t)buf);
+ dcache_wbinv_poc((vm_offset_t)buf, pa, count);
bus_dmamap_sync(bi->pagelist_dma_tag, bi->pagelist_dma_map,
BUS_DMASYNC_PREWRITE);
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