Author: andrew
Date: Wed May 11 14:59:54 2016
New Revision: 299457
URL: https://svnweb.freebsd.org/changeset/base/299457
Log:
Add data barriers to the arm64 bus_dmamap_sync function. We need these
to ensure ordering between the CPU and device. As the CPU and DMA target
may be in different shareability domains they need to be full system
barriers.
Obtained from: ABT Systems Ltd
Sponsored by: The FreeBSD Foundation
Modified:
head/sys/arm64/arm64/busdma_bounce.c
Modified: head/sys/arm64/arm64/busdma_bounce.c
==============================================================================
--- head/sys/arm64/arm64/busdma_bounce.c Wed May 11 14:38:27 2016
(r299456)
+++ head/sys/arm64/arm64/busdma_bounce.c Wed May 11 14:59:54 2016
(r299457)
@@ -770,8 +770,11 @@ bounce_bus_dmamap_sync(bus_dma_tag_t dma
struct bounce_page *bpage;
vm_offset_t datavaddr, tempvaddr;
- if (map == NULL || (bpage = STAILQ_FIRST(&map->bpages)) == NULL)
+ if (map == NULL || (bpage = STAILQ_FIRST(&map->bpages)) == NULL) {
+ /* Wait for any memory access to complete */
+ dsb(sy);
return;
+ }
/*
* XXX ARM64TODO:
@@ -801,9 +804,19 @@ bounce_bus_dmamap_sync(bus_dma_tag_t dma
bpage = STAILQ_NEXT(bpage, links);
}
dmat->bounce_zone->total_bounced++;
+
+ /*
+ * Wait for the bcopy to complete before any DMA operations.
+ */
+ dsb(sy);
}
if ((op & BUS_DMASYNC_POSTREAD) != 0) {
+ /*
+ * Wait for any DMA operations to complete before the bcopy.
+ */
+ dsb(sy);
+
while (bpage != NULL) {
tempvaddr = 0;
datavaddr = bpage->datavaddr;
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