Author: adrian
Date: Thu Jul 6 04:56:23 2017
New Revision: 320704
URL: https://svnweb.freebsd.org/changeset/base/320704
Log:
[ar724x] put in explicit memory barriers now that read/write register no
longer
implicitly do them.
They were removed as part of my "fix this to actually work" a few commits
ago in this file.
Tested:
* AP93, AR7240 + AR9280 PCI
Modified:
head/sys/mips/atheros/ar724x_pci.c
Modified: head/sys/mips/atheros/ar724x_pci.c
==============================================================================
--- head/sys/mips/atheros/ar724x_pci.c Thu Jul 6 04:30:06 2017
(r320703)
+++ head/sys/mips/atheros/ar724x_pci.c Thu Jul 6 04:56:23 2017
(r320704)
@@ -104,10 +104,12 @@ ar724x_pci_write(uint32_t reg, uint32_t offset, uint32
else
mask = 0xffffffff;
+ rmb();
val = ATH_READ_REG(reg + (offset & ~3));
val &= ~(mask << shift);
val |= ((data & mask) << shift);
ATH_WRITE_REG(reg + (offset & ~3), val);
+ wmb();
dprintf("%s: %#x/%#x addr=%#x, data=%#x(%#x), bytes=%d\n", __func__,
reg, reg + (offset & ~3), offset, data, val, bytes);
@@ -133,6 +135,7 @@ ar724x_pci_read_config(device_t dev, u_int bus, u_int
dprintf("%s: tag (%x, %x, %x) reg %d(%d)\n", __func__, bus, slot,
func, reg, bytes);
+ rmb();
if ((bus == 0) && (slot == 0) && (func == 0))
data = ATH_READ_REG(AR724X_PCI_CFG_BASE + (reg & ~3));
else
@@ -166,6 +169,9 @@ ar724x_pci_write_config(device_t dev, u_int bus, u_int
* map is for this device. Without it, it'll think the memory
* map is 32 bits wide, the PCI code will then end up thinking
* the register window is '0' and fail to allocate resources.
+ *
+ * Note: Test on AR7241/AR7242/AR9344! Those use a WAR value of
+ * 0x1000ffff.
*/
if (reg == PCIR_BAR(0) && bytes == 4
&& ar71xx_soc == AR71XX_SOC_AR7240
@@ -284,6 +290,7 @@ ar724x_pci_fixup(device_t dev, long flash_addr, int le
bar0 = ar724x_pci_read_config(dev, 0, 0, 0, PCIR_BAR(0), 4);
/* Write temporary BAR0 to map the NIC into a fixed location */
+ /* XXX AR7240: 0xffff; 7241/7242/9344: 0x1000ffff */
ar724x_pci_write_config(dev, 0, 0, 0, PCIR_BAR(0),
AR71XX_PCI_MEM_BASE, 4);
@@ -299,7 +306,7 @@ ar724x_pci_fixup(device_t dev, long flash_addr, int le
val |= (*cal_data++) << 16;
if (bootverbose)
- printf(" 0x%08x=0x%04x\n", reg, val);
+ printf(" 0x%08x=0x%08x\n", reg, val);
/* Write eeprom fixup data to device memory */
ATH_WRITE_REG(AR71XX_PCI_MEM_BASE + reg, val);
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