Author: cem
Date: Mon Sep 11 20:42:07 2017
New Revision: 323463
URL: https://svnweb.freebsd.org/changeset/base/323463
Log:
MCA: Rename AMD MISC bits/masks
They apply to all AMD MCAi_MISC0 registers, not just MCA4 (NB).
No functional change.
Sponsored by: Dell EMC Isilon
Modified:
head/sys/x86/include/specialreg.h
head/sys/x86/x86/mca.c
Modified: head/sys/x86/include/specialreg.h
==============================================================================
--- head/sys/x86/include/specialreg.h Mon Sep 11 20:41:25 2017
(r323462)
+++ head/sys/x86/include/specialreg.h Mon Sep 11 20:42:07 2017
(r323463)
@@ -715,22 +715,22 @@
#define MC_CTL2_THRESHOLD 0x0000000000007fff
#define MC_CTL2_CMCI_EN 0x0000000040000000
#define MC_AMDNB_BANK 4
-#define MC_MISC_AMDNB_VAL 0x8000000000000000 /* Counter
presence valid */
-#define MC_MISC_AMDNB_CNTP 0x4000000000000000 /* Counter
present */
-#define MC_MISC_AMDNB_LOCK 0x2000000000000000 /* Register
locked */
-#define MC_MISC_AMDNB_INTP 0x1000000000000000 /* Int. type
can generate interrupts */
-#define MC_MISC_AMDNB_LVT_MASK 0x00f0000000000000 /* Extended LVT
offset */
-#define MC_MISC_AMDNB_LVT_SHIFT 52
-#define MC_MISC_AMDNB_CNTEN 0x0008000000000000 /* Counter
enabled */
-#define MC_MISC_AMDNB_INT_MASK 0x0006000000000000 /* Interrupt
type */
-#define MC_MISC_AMDNB_INT_LVT 0x0002000000000000 /* Interrupt
via Extended LVT */
-#define MC_MISC_AMDNB_INT_SMI 0x0004000000000000 /* SMI */
-#define MC_MISC_AMDNB_OVERFLOW 0x0001000000000000 /* Counter
overflow */
-#define MC_MISC_AMDNB_CNT_MASK 0x00000fff00000000 /* Counter
value */
-#define MC_MISC_AMDNB_CNT_SHIFT 32
-#define MC_MISC_AMDNB_CNT_MAX 0xfff
-#define MC_MISC_AMDNB_PTR_MASK 0x00000000ff000000 /* Pointer to
additional registers */
-#define MC_MISC_AMDNB_PTR_SHIFT 24
+#define MC_MISC_AMD_VAL 0x8000000000000000 /* Counter
presence valid */
+#define MC_MISC_AMD_CNTP 0x4000000000000000 /* Counter
present */
+#define MC_MISC_AMD_LOCK 0x2000000000000000 /* Register
locked */
+#define MC_MISC_AMD_INTP 0x1000000000000000 /* Int. type
can generate interrupts */
+#define MC_MISC_AMD_LVT_MASK 0x00f0000000000000 /* Extended LVT
offset */
+#define MC_MISC_AMD_LVT_SHIFT 52
+#define MC_MISC_AMD_CNTEN 0x0008000000000000 /* Counter
enabled */
+#define MC_MISC_AMD_INT_MASK 0x0006000000000000 /* Interrupt
type */
+#define MC_MISC_AMD_INT_LVT 0x0002000000000000 /* Interrupt
via Extended LVT */
+#define MC_MISC_AMD_INT_SMI 0x0004000000000000 /* SMI */
+#define MC_MISC_AMD_OVERFLOW 0x0001000000000000 /* Counter
overflow */
+#define MC_MISC_AMD_CNT_MASK 0x00000fff00000000 /* Counter
value */
+#define MC_MISC_AMD_CNT_SHIFT 32
+#define MC_MISC_AMD_CNT_MAX 0xfff
+#define MC_MISC_AMD_PTR_MASK 0x00000000ff000000 /* Pointer to
additional registers */
+#define MC_MISC_AMD_PTR_SHIFT 24
/*
* The following four 3-byte registers control the non-cacheable regions.
Modified: head/sys/x86/x86/mca.c
==============================================================================
--- head/sys/x86/x86/mca.c Mon Sep 11 20:41:25 2017 (r323462)
+++ head/sys/x86/x86/mca.c Mon Sep 11 20:42:07 2017 (r323463)
@@ -649,17 +649,17 @@ amd_thresholding_update(enum scan_mode mode, int bank,
("%s: unexpected bank %d", __func__, bank));
cc = &amd_et_state[PCPU_GET(cpuid)];
misc = rdmsr(MSR_MC_MISC(bank));
- count = (misc & MC_MISC_AMDNB_CNT_MASK) >> MC_MISC_AMDNB_CNT_SHIFT;
- count = count - (MC_MISC_AMDNB_CNT_MAX - cc->cur_threshold);
+ count = (misc & MC_MISC_AMD_CNT_MASK) >> MC_MISC_AMD_CNT_SHIFT;
+ count = count - (MC_MISC_AMD_CNT_MAX - cc->cur_threshold);
new_threshold = update_threshold(mode, valid, cc->last_intr, count,
- cc->cur_threshold, MC_MISC_AMDNB_CNT_MAX);
+ cc->cur_threshold, MC_MISC_AMD_CNT_MAX);
cc->cur_threshold = new_threshold;
- misc &= ~MC_MISC_AMDNB_CNT_MASK;
- misc |= (uint64_t)(MC_MISC_AMDNB_CNT_MAX - cc->cur_threshold)
- << MC_MISC_AMDNB_CNT_SHIFT;
- misc &= ~MC_MISC_AMDNB_OVERFLOW;
+ misc &= ~MC_MISC_AMD_CNT_MASK;
+ misc |= (uint64_t)(MC_MISC_AMD_CNT_MAX - cc->cur_threshold)
+ << MC_MISC_AMD_CNT_SHIFT;
+ misc &= ~MC_MISC_AMD_OVERFLOW;
wrmsr(MSR_MC_MISC(bank), misc);
if (mode == CMCI && valid)
cc->last_intr = time_uptime;
@@ -971,15 +971,15 @@ amd_thresholding_start(struct amd_et_state *cc)
KASSERT(amd_elvt >= 0, ("ELVT offset is not set"));
misc = rdmsr(MSR_MC_MISC(MC_AMDNB_BANK));
- misc &= ~MC_MISC_AMDNB_INT_MASK;
- misc |= MC_MISC_AMDNB_INT_LVT;
- misc &= ~MC_MISC_AMDNB_LVT_MASK;
- misc |= (uint64_t)amd_elvt << MC_MISC_AMDNB_LVT_SHIFT;
- misc &= ~MC_MISC_AMDNB_CNT_MASK;
- misc |= (uint64_t)(MC_MISC_AMDNB_CNT_MAX - cc->cur_threshold)
- << MC_MISC_AMDNB_CNT_SHIFT;
- misc &= ~MC_MISC_AMDNB_OVERFLOW;
- misc |= MC_MISC_AMDNB_CNTEN;
+ misc &= ~MC_MISC_AMD_INT_MASK;
+ misc |= MC_MISC_AMD_INT_LVT;
+ misc &= ~MC_MISC_AMD_LVT_MASK;
+ misc |= (uint64_t)amd_elvt << MC_MISC_AMD_LVT_SHIFT;
+ misc &= ~MC_MISC_AMD_CNT_MASK;
+ misc |= (uint64_t)(MC_MISC_AMD_CNT_MAX - cc->cur_threshold)
+ << MC_MISC_AMD_CNT_SHIFT;
+ misc &= ~MC_MISC_AMD_OVERFLOW;
+ misc |= MC_MISC_AMD_CNTEN;
wrmsr(MSR_MC_MISC(MC_AMDNB_BANK), misc);
}
@@ -992,15 +992,15 @@ amd_thresholding_init(void)
/* The counter must be valid and present. */
misc = rdmsr(MSR_MC_MISC(MC_AMDNB_BANK));
- if ((misc & (MC_MISC_AMDNB_VAL | MC_MISC_AMDNB_CNTP)) !=
- (MC_MISC_AMDNB_VAL | MC_MISC_AMDNB_CNTP)) {
+ if ((misc & (MC_MISC_AMD_VAL | MC_MISC_AMD_CNTP)) !=
+ (MC_MISC_AMD_VAL | MC_MISC_AMD_CNTP)) {
printf("%s: 0x%jx: !valid | !present\n", __func__,
(uintmax_t)misc);
return;
}
/* The register should not be locked. */
- if ((misc & MC_MISC_AMDNB_LOCK) != 0) {
+ if ((misc & MC_MISC_AMD_LOCK) != 0) {
printf("%s: 0x%jx: locked\n", __func__, (uintmax_t)misc);
return;
}
@@ -1009,7 +1009,7 @@ amd_thresholding_init(void)
* If counter is enabled then either the firmware or another CPU
* has already claimed it.
*/
- if ((misc & MC_MISC_AMDNB_CNTEN) != 0) {
+ if ((misc & MC_MISC_AMD_CNTEN) != 0) {
printf("%s: 0x%jx: count already enabled\n", __func__,
(uintmax_t)misc);
return;
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