Author: np
Date: Thu May 24 08:21:43 2018
New Revision: 334138
URL: https://svnweb.freebsd.org/changeset/base/334138
Log:
cxgbe(4): Make FW4_ACK a shared CPL. ETHOFLD in the base driver will
use it for per-flow rate limiting.
Sponsored by: Chelsio Communications
Modified:
head/sys/dev/cxgbe/adapter.h
head/sys/dev/cxgbe/common/t4_msg.h
head/sys/dev/cxgbe/t4_sge.c
head/sys/dev/cxgbe/tom/t4_cpl_io.c
Modified: head/sys/dev/cxgbe/adapter.h
==============================================================================
--- head/sys/dev/cxgbe/adapter.h Thu May 24 08:02:11 2018
(r334137)
+++ head/sys/dev/cxgbe/adapter.h Thu May 24 08:21:43 2018
(r334138)
@@ -372,7 +372,7 @@ enum {
CPL_COOKIE_DDP1,
CPL_COOKIE_TOM,
CPL_COOKIE_HASHFILTER,
- CPL_COOKIE_AVAILABLE2,
+ CPL_COOKIE_ETHOFLD,
CPL_COOKIE_AVAILABLE3,
NUM_CPL_COOKIES = 8 /* Limited by M_COOKIE. Do not increase. */
Modified: head/sys/dev/cxgbe/common/t4_msg.h
==============================================================================
--- head/sys/dev/cxgbe/common/t4_msg.h Thu May 24 08:02:11 2018
(r334137)
+++ head/sys/dev/cxgbe/common/t4_msg.h Thu May 24 08:21:43 2018
(r334138)
@@ -2751,6 +2751,30 @@ enum {
CPL_FW4_ACK_FLAGS_FLOWC = 0x4, /* fw_flowc_wr complete */
};
+#define S_CPL_FW4_ACK_OPCODE 24
+#define M_CPL_FW4_ACK_OPCODE 0xff
+#define V_CPL_FW4_ACK_OPCODE(x) ((x) << S_CPL_FW4_ACK_OPCODE)
+#define G_CPL_FW4_ACK_OPCODE(x) \
+ (((x) >> S_CPL_FW4_ACK_OPCODE) & M_CPL_FW4_ACK_OPCODE)
+
+#define S_CPL_FW4_ACK_FLOWID 0
+#define M_CPL_FW4_ACK_FLOWID 0xffffff
+#define V_CPL_FW4_ACK_FLOWID(x) ((x) << S_CPL_FW4_ACK_FLOWID)
+#define G_CPL_FW4_ACK_FLOWID(x) \
+ (((x) >> S_CPL_FW4_ACK_FLOWID) & M_CPL_FW4_ACK_FLOWID)
+
+#define S_CPL_FW4_ACK_CR 24
+#define M_CPL_FW4_ACK_CR 0xff
+#define V_CPL_FW4_ACK_CR(x) ((x) << S_CPL_FW4_ACK_CR)
+#define G_CPL_FW4_ACK_CR(x) (((x) >> S_CPL_FW4_ACK_CR) & M_CPL_FW4_ACK_CR)
+
+#define S_CPL_FW4_ACK_SEQVAL 0
+#define M_CPL_FW4_ACK_SEQVAL 0x1
+#define V_CPL_FW4_ACK_SEQVAL(x) ((x) << S_CPL_FW4_ACK_SEQVAL)
+#define G_CPL_FW4_ACK_SEQVAL(x) \
+ (((x) >> S_CPL_FW4_ACK_SEQVAL) & M_CPL_FW4_ACK_SEQVAL)
+#define F_CPL_FW4_ACK_SEQVAL V_CPL_FW4_ACK_SEQVAL(1U)
+
struct cpl_fw6_msg {
RSS_HDR
u8 opcode;
Modified: head/sys/dev/cxgbe/t4_sge.c
==============================================================================
--- head/sys/dev/cxgbe/t4_sge.c Thu May 24 08:02:11 2018 (r334137)
+++ head/sys/dev/cxgbe/t4_sge.c Thu May 24 08:21:43 2018 (r334138)
@@ -290,6 +290,7 @@ cpl_handler_t set_tcb_rpl_handlers[NUM_CPL_COOKIES];
cpl_handler_t l2t_write_rpl_handlers[NUM_CPL_COOKIES];
cpl_handler_t act_open_rpl_handlers[NUM_CPL_COOKIES];
cpl_handler_t abort_rpl_rss_handlers[NUM_CPL_COOKIES];
+cpl_handler_t fw4_ack_handlers[NUM_CPL_COOKIES];
void
t4_register_an_handler(an_handler_t h)
@@ -402,6 +403,23 @@ abort_rpl_rss_handler(struct sge_iq *iq, const struct
return (abort_rpl_rss_handlers[cookie](iq, rss, m));
}
+static int
+fw4_ack_handler(struct sge_iq *iq, const struct rss_header *rss, struct mbuf
*m)
+{
+ struct adapter *sc = iq->adapter;
+ const struct cpl_fw4_ack *cpl = (const void *)(rss + 1);
+ unsigned int tid = G_CPL_FW4_ACK_FLOWID(be32toh(OPCODE_TID(cpl)));
+ u_int cookie;
+
+ MPASS(m == NULL);
+ if (is_etid(sc, tid))
+ cookie = CPL_COOKIE_ETHOFLD;
+ else
+ cookie = CPL_COOKIE_TOM;
+
+ return (fw4_ack_handlers[cookie](iq, rss, m));
+}
+
static void
t4_init_shared_cpl_handlers(void)
{
@@ -410,6 +428,7 @@ t4_init_shared_cpl_handlers(void)
t4_register_cpl_handler(CPL_L2T_WRITE_RPL, l2t_write_rpl_handler);
t4_register_cpl_handler(CPL_ACT_OPEN_RPL, act_open_rpl_handler);
t4_register_cpl_handler(CPL_ABORT_RPL_RSS, abort_rpl_rss_handler);
+ t4_register_cpl_handler(CPL_FW4_ACK, fw4_ack_handler);
}
void
@@ -434,6 +453,9 @@ t4_register_shared_cpl_handler(int opcode, cpl_handler
break;
case CPL_ABORT_RPL_RSS:
loc = (uintptr_t *)&abort_rpl_rss_handlers[cookie];
+ break;
+ case CPL_FW4_ACK:
+ loc = (uintptr_t *)&fw4_ack_handlers[cookie];
break;
default:
MPASS(0);
Modified: head/sys/dev/cxgbe/tom/t4_cpl_io.c
==============================================================================
--- head/sys/dev/cxgbe/tom/t4_cpl_io.c Thu May 24 08:02:11 2018
(r334137)
+++ head/sys/dev/cxgbe/tom/t4_cpl_io.c Thu May 24 08:21:43 2018
(r334138)
@@ -1725,30 +1725,6 @@ do_rx_data(struct sge_iq *iq, const struct rss_header
return (0);
}
-#define S_CPL_FW4_ACK_OPCODE 24
-#define M_CPL_FW4_ACK_OPCODE 0xff
-#define V_CPL_FW4_ACK_OPCODE(x) ((x) << S_CPL_FW4_ACK_OPCODE)
-#define G_CPL_FW4_ACK_OPCODE(x) \
- (((x) >> S_CPL_FW4_ACK_OPCODE) & M_CPL_FW4_ACK_OPCODE)
-
-#define S_CPL_FW4_ACK_FLOWID 0
-#define M_CPL_FW4_ACK_FLOWID 0xffffff
-#define V_CPL_FW4_ACK_FLOWID(x) ((x) << S_CPL_FW4_ACK_FLOWID)
-#define G_CPL_FW4_ACK_FLOWID(x) \
- (((x) >> S_CPL_FW4_ACK_FLOWID) & M_CPL_FW4_ACK_FLOWID)
-
-#define S_CPL_FW4_ACK_CR 24
-#define M_CPL_FW4_ACK_CR 0xff
-#define V_CPL_FW4_ACK_CR(x) ((x) << S_CPL_FW4_ACK_CR)
-#define G_CPL_FW4_ACK_CR(x) (((x) >> S_CPL_FW4_ACK_CR) & M_CPL_FW4_ACK_CR)
-
-#define S_CPL_FW4_ACK_SEQVAL 0
-#define M_CPL_FW4_ACK_SEQVAL 0x1
-#define V_CPL_FW4_ACK_SEQVAL(x) ((x) << S_CPL_FW4_ACK_SEQVAL)
-#define G_CPL_FW4_ACK_SEQVAL(x) \
- (((x) >> S_CPL_FW4_ACK_SEQVAL) & M_CPL_FW4_ACK_SEQVAL)
-#define F_CPL_FW4_ACK_SEQVAL V_CPL_FW4_ACK_SEQVAL(1U)
-
static int
do_fw4_ack(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m)
{
@@ -1956,7 +1932,7 @@ t4_init_cpl_io_handlers(void)
t4_register_shared_cpl_handler(CPL_ABORT_RPL_RSS, do_abort_rpl,
CPL_COOKIE_TOM);
t4_register_cpl_handler(CPL_RX_DATA, do_rx_data);
- t4_register_cpl_handler(CPL_FW4_ACK, do_fw4_ack);
+ t4_register_shared_cpl_handler(CPL_FW4_ACK, do_fw4_ack, CPL_COOKIE_TOM);
}
void
@@ -1968,7 +1944,7 @@ t4_uninit_cpl_io_handlers(void)
t4_register_cpl_handler(CPL_ABORT_REQ_RSS, NULL);
t4_register_cpl_handler(CPL_ABORT_RPL_RSS, NULL);
t4_register_cpl_handler(CPL_RX_DATA, NULL);
- t4_register_cpl_handler(CPL_FW4_ACK, NULL);
+ t4_register_shared_cpl_handler(CPL_FW4_ACK, NULL, CPL_COOKIE_TOM);
}
/*
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