Author: ian
Date: Fri Feb 13 00:12:21 2015
New Revision: 278645
URL: https://svnweb.freebsd.org/changeset/base/278645

Log:
  MFC r276444, r276445, r276470:
  
   Fix a paste-o in dcache_inv_pou_all().
  
   Change the order of operations for the initial cache setup.
  
   A couple small fixes to make clang 3.5 happy... Move END(sigcode)
   and other misplace ENTRY/END macros.

Modified:
  stable/10/sys/arm/arm/cpu_asm-v6.S
  stable/10/sys/arm/arm/locore-v6.S
Directory Properties:
  stable/10/   (props changed)

Modified: stable/10/sys/arm/arm/cpu_asm-v6.S
==============================================================================
--- stable/10/sys/arm/arm/cpu_asm-v6.S  Fri Feb 13 00:08:32 2015        
(r278644)
+++ stable/10/sys/arm/arm/cpu_asm-v6.S  Fri Feb 13 00:12:21 2015        
(r278645)
@@ -106,7 +106,7 @@ ASENTRY_NP(dcache_inv_pou_all)
        bx      lr
 #else
        mrc     CP15_CLIDR(r0)
-       ands    r0, r0, #0x07000000
+       ands    r0, r0, #0x38000000
        mov     r0, r0, lsr #26         /* Get LoUU (naturally aligned) */
        beq     4f
 

Modified: stable/10/sys/arm/arm/locore-v6.S
==============================================================================
--- stable/10/sys/arm/arm/locore-v6.S   Fri Feb 13 00:08:32 2015        
(r278644)
+++ stable/10/sys/arm/arm/locore-v6.S   Fri Feb 13 00:12:21 2015        
(r278645)
@@ -84,11 +84,9 @@ ASENTRY_NP(_start)
         */
        mrc     CP15_SCTLR(r7)
        tst     r7, #CPU_CONTROL_DC_ENABLE
-       beq     1f
-       bic     r7, #CPU_CONTROL_DC_ENABLE
-       mcr     CP15_SCTLR(r7)
-       ISB
-       bl      dcache_wbinv_poc_all
+       blne    dcache_wbinv_poc_all
+
+       /* ! Do not write to memory between wbinv and disabling cache ! */
 
        /*
         * Now there are no dirty lines, but there may still be lines marked
@@ -96,6 +94,7 @@ ASENTRY_NP(_start)
         * before setting up new page tables and re-enabling the mmu.
         */
 1:     
+       bic     r7, #CPU_CONTROL_DC_ENABLE
        bic     r7, #CPU_CONTROL_MMU_ENABLE
        bic     r7, #CPU_CONTROL_IC_ENABLE
        bic     r7, #CPU_CONTROL_UNAL_ENABLE
@@ -340,7 +339,7 @@ END(reinit_mmu)
  *
  * Addresses must be 1MiB aligned
  */
-ASENTRY_NP(build_pagetables)
+build_pagetables:
        /* Set the required page attributed */
 #if defined(ARM_NEW_PMAP)
        ldr     r4, =PTE1_V|PTE1_A|PTE1_AP_KRW|TEX1_CLASS_0
@@ -521,6 +520,7 @@ ENTRY_NP(sigcode)
 
        /* Branch back to retry SYS_sigreturn */
        b       . - 16
+END(sigcode)
 
        .word   SYS_sigreturn
        .word   SYS_exit
@@ -533,5 +533,5 @@ ENTRY_NP(sigcode)
        .global szsigcode
 szsigcode:
        .long esigcode-sigcode
-END(sigcode)
+
 /* End of locore.S */
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