[swift-dev] [Swift CI] Build Still Failing: 1. OSS - Swift (Tools Opt+Assert, Stdlib Opt+DebInfo+Assert, Resilience) - macOS (master) #119

Tue, 28 Nov 2017 03:52:35 -0800

New issue found!

Title: Report

[FAILURE] oss-swift_tools-RA_stdlib-RDA_test-macos-resilience [#119]

Build URL:https://ci.swift.org/job/oss-swift_tools-RA_stdlib-RDA_test-macos-resilience/119/
Project:oss-swift_tools-RA_stdlib-RDA_test-macos-resilience
Date of build:Tue, 28 Nov 2017 03:47:00 -0600
Build duration:2 hr 5 min

Identified problems:

  • Regression test failed: This build failed because a regression test in the test suite FAILed. Below is a list of all errors:

Changes

  • Commit 6482c327b367cf5cba32294b9e2be8e60f610420 by github:

    When the new build system fails with build

    • edit: include/llbuild/BuildSystem/BuildSystemFrontend.h
    • edit: products/libllbuild/BuildSystem-C-API.cpp

  • Commit 3f3d784144129ab20f582df8268e812ad4561714 by ungar:

    Factor code from tools & move input conversion.

    • edit: lib/Frontend/CompilerInvocation.cpp
    • edit: lib/Migrator/Migrator.cpp
    • edit: lib/FrontendTool/FrontendTool.cpp
    • edit: tools/sil-nm/SILNM.cpp
    • edit: tools/swift-ide-test/swift-ide-test.cpp
    • edit: tools/SourceKit/lib/SwiftLang/SwiftASTManager.cpp
    • edit: tools/sil-llvm-gen/SILLLVMGen.cpp
    • edit: lib/Frontend/FrontendOptions.cpp
    • edit: include/swift/Frontend/FrontendOptions.h
    • edit: tools/sil-opt/SILOpt.cpp
    • edit: tools/sil-func-extractor/SILFunctionExtractor.cpp
    • edit: include/swift/AST/DiagnosticsFrontend.def
    • edit: include/swift/Frontend/Frontend.h
    • edit: lib/Frontend/Frontend.cpp

  • Commit ad217f7ce610335e10b8fd101d7b7b21ed9f902a by ungar:

    Fix StringRef parameter declaration.

    • edit: include/swift/Frontend/Frontend.h

  • Commit 70ddd3d53b3168af25b04a0bd2ac47aba0fa2ca8 by ungar:

    Read command line arguments even if filelist is present.

    • edit: lib/Frontend/CompilerInvocation.cpp

  • Commit 6a860e38f018a8ae50f6d65f343ddc59b0321f3c by ungar:

    Don’t clearPrimaryInputs for swift-ide-test, set primary to first file.

    • edit: tools/swift-ide-test/swift-ide-test.cpp

  • Commit 07dfa263cd8eae153a578d8b5c5fc19da1305cea by ungar:

    Keep separate lists instead of same file twice in one list.

    • edit: lib/Frontend/CompilerInvocation.cpp

  • Commit 26537ea26cf402eaf5b99c7254fcb9cae3865dea by ungar:

    Address Jordan’s comments:

    • edit: tools/SourceKit/lib/SwiftLang/SwiftCompletion.cpp
    • edit: lib/Frontend/FrontendOptions.cpp
    • edit: lib/Migrator/Migrator.cpp
    • edit: include/swift/Frontend/FrontendOptions.h
    • edit: tools/SourceKit/lib/SwiftLang/SwiftIndexing.cpp
    • edit: lib/FrontendTool/FrontendTool.cpp
    • edit: tools/SourceKit/lib/SwiftLang/SwiftASTManager.cpp
    • edit: lib/Frontend/CompilerInvocation.cpp
    • edit: tools/driver/modulewrap_main.cpp

  • Commit 0b39a883c2aa676092222b096fcee38b20a304e7 by ungar:

    Fix capitalization of setUpForFileAt

    • edit: lib/Frontend/Frontend.cpp
    • edit: include/swift/Frontend/Frontend.h

  • Commit 835d1a221c58ee6b9ee8adf0839e03a5ad01ef9c by dave:

    NFC: Use 'enum class' for TypeResolutionFlags

    • edit: lib/Sema/TypeCheckGeneric.cpp
    • edit: lib/Sema/TypeCheckStmt.cpp
    • edit: lib/Sema/ITCType.cpp
    • edit: lib/Sema/TypeChecker.h
    • edit: lib/Sema/ITCDecl.cpp
    • edit: lib/Sema/TypeCheckAttr.cpp
    • edit: lib/Sema/TypeCheckType.cpp
    • edit: lib/Sema/TypeChecker.cpp
    • edit: lib/Sema/TypeCheckPattern.cpp
    • edit: lib/Sema/ConstraintSystem.cpp
    • edit: lib/Sema/TypeCheckConstraints.cpp
    • edit: lib/Sema/CSGen.cpp
    • edit: lib/Sema/TypeCheckDecl.cpp

  • Commit 390d4464ad4174d569d94cd5cec1c5c9fa494694 by natecook:

    Support larger integers in String(_:radix:)

    • edit: stdlib/public/core/StringLegacy.swift

  • Commit abb75bca1a36ae2ce76586edab87dae1f308de5d by natecook:

    Allow large integer literals for DoubleWidth

    • edit: stdlib/public/core/DoubleWidth.swift.gyb

  • Commit 5dbfa2d9478cea7ea3369279a51552a04f405c7e by natecook:

    Update tests for larger integer sizes

    • edit: test/stdlib/Integers.swift.gyb
    • add: test/stdlib/DoubleWidth.swift

  • Commit 01891c0ca8e207deca1a290b04a747c22d651ea0 by github:

    Clarify Associated Type Inference and SE-0108

    • edit: docs/GenericsManifesto.md

  • Commit 3e04f21a41fdbc040bdd4f9bac72b3c2af846889 by aschwaighofer:

    SIL: Remove EnableGuaranteedClosureContext now that it is the default

    • edit: lib/SILGen/SILGenFunction.cpp
    • edit: lib/SILGen/SILGenProlog.cpp
    • edit: lib/SILGen/SILGenExpr.cpp
    • edit: lib/SILGen/SILGenThunk.cpp
    • edit: include/swift/SIL/TypeLowering.h
    • edit: lib/SILGen/SILGenApply.cpp
    • edit: lib/SIL/SILFunctionType.cpp
    • edit: lib/SILOptimizer/IPO/CapturePropagation.cpp
    • edit: lib/SILGen/SILGenBridging.cpp
    • edit: include/swift/AST/SILOptions.h
    • edit: lib/Frontend/CompilerInvocation.cpp
    • edit: lib/SILGen/SILGenPoly.cpp

  • Commit 6de8011be6e187c156aa1e78f40fa75a51afed46 by mgottesman:

    [+0-normal] Use Scope::popPreservingValue instead of using a hand-rolled

    • edit: lib/SILGen/SILGenStmt.cpp

  • Commit 48d11bd54021a31df8df5ec63d83cafc0c60c9fe by aschwaighofer:

    stdlib: Fix test cases Dictionary.swift and Set.swift

    • edit: validation-test/stdlib/Dictionary.swift
    • edit: validation-test/stdlib/Set.swift

  • Commit 588ac6b3e8335a584d12b7fb17e9e9028198d2f2 by github:

    libSyntax: add several elementary nodes. (#13085)

    • edit: test/Syntax/Outputs/round_trip_parse_gen.swift.withkinds
    • edit: utils/gyb_syntax_support/ExprNodes.py
    • edit: lib/Syntax/SyntaxFactory.cpp.gyb
    • edit: lib/Syntax/SyntaxParsingContext.cpp
    • edit: include/swift/Syntax/SyntaxParsingContext.h
    • edit: lib/Parse/ParseExpr.cpp

  • Commit 3d6e9cc6299aa2be38e1a1e9726f0a8ea1d1762b by jordan_rose:

    [Serialization] Use a helper to get dependencies from requirements

    • edit: lib/Serialization/Serialization.cpp

  • Commit 6c3a25656f2e8709439eff7da6e25531ecf6aa80 by jordan_rose:

    [test] Add some tests for non-deserializable generic requirements

    • edit: test/Serialization/Recovery/typedefs.swift

  • Commit 9cac094f890610333899399bf7d17fc71f50e26d by jordan_rose:

    [Serialization] Recover if an enum's generic requirements are broken

    • edit: test/Serialization/Recovery/typedefs-in-enums.swift
    • edit: lib/Serialization/Serialization.cpp

  • Commit df0fd6abfb37ab32c3d10af56e747a241b8b1077 by pyaskevich:

    [ConstraintSystem] Improve type parameter requirement locators

    • edit: lib/Sema/ConstraintLocator.cpp
    • edit: lib/Sema/ConstraintLocator.h
    • edit: lib/Sema/ConstraintSystem.cpp

  • Commit 094091c8d79b4fe5df3ab9bccac1b14926ae9b53 by aschwaighofer:

    stdlib: Fix UXPass in ArrayNew.swift.gyb

    • edit: validation-test/stdlib/ArrayNew.swift.gyb

  • Commit 66a2f5d05dcdebd7bb1685c03cc926dcb38154cf by aschwaighofer:

    Disable test that fails on linux asan bot rdar://26498438

    • edit: validation-test/compiler_crashers_2/0121-rdar26498438.swift

  • Commit 2c857dc6a8258d0f6a1373a0e5855779fd41d302 by shajrawi:

    copy_addr outline: fix a bug wherein a record type contains a resilient

    • edit: lib/IRGen/ResilientTypeInfo.h

  • Commit 8342f77bc4773e8e72eb6143b77bb1b7421aeb18 by dgregor:

    [Overloading] Adjust @autoclosure parameter types to their result types.

    • edit: lib/Sema/CSRanking.cpp
    • edit: test/Constraints/overload.swift

  • Commit a6796e06a65aeb5d6ca4c23496ecd4dc893ac9c0 by github:

    Changed the --enable-tsan-runtime option to use the enable action like

    • edit: utils/build_swift/tests/expected_options.py
    • edit: utils/build_swift/driver_arguments.py

  • Commit 567e3596e5a1a7530335eb3985a7385e7c7b22e0 by mgottesman:

    [+0-all-args] Fix address only for-each emission to not hack around

    • edit: lib/SILGen/SILGenStmt.cpp

  • Commit 35fd24ed74dc74db12a353bae9c8a9e8b0afbd4f by mgottesman:

    [+0-all-args] Create SILGenBuilder::createTuple().

    • edit: lib/SILGen/SILGenExpr.cpp
    • edit: lib/SILGen/SILGenBuilder.h
    • edit: lib/SILGen/SILGenBridging.cpp
    • edit: lib/SILGen/SILGenBuilder.cpp

  • Commit 549efbc240f923150ee330b79ddc7c3bd6cb4fb0 by rjmccall:

    Don't naively apply the bridging peephole to AnyObject? -> Any? ->

    • edit: lib/SILGen/SILGenConvert.cpp
    • edit: test/SILGen/objc_bridging_peephole.swift
    • edit: lib/SILGen/SILGenBridging.cpp
    • edit: test/Inputs/clang-importer-sdk/usr/include/Foundation.h

  • Commit 1a5b7e1e8eee5b4c14b44c7d769441689aec49b6 by mgottesman:

    [+0-all-args] Change SGF::emitUncheckedGetOptionalValueFrom to use

    • edit: lib/SILGen/SILGenBuilder.cpp
    • edit: lib/SILGen/SILGenConvert.cpp

  • Commit 036321546b41f2e00eefa8caa42f27cadd49d36d by xi_ge:

    libSyntax: Support tuple _expression_.

    • edit: lib/Parse/ParseExpr.cpp
    • edit: test/Syntax/round_trip_parse_gen.swift
    • edit: lib/Parse/Parser.cpp
    • edit: utils/gyb_syntax_support/ExprNodes.py
    • edit: test/Syntax/Outputs/round_trip_parse_gen.swift.withkinds

  • Commit 966f543003e6d9b05f12a8dff7fd7f4562204274 by dgregor:

    [IRGen] Factor out binding of local type metadata for self witness

    • edit: lib/IRGen/GenProto.cpp
    • edit: lib/IRGen/GenProto.h
    • edit: lib/IRGen/GenOpaque.h
    • edit: lib/IRGen/LocalTypeData.cpp
    • edit: lib/IRGen/IRGenFunction.h

  • Commit 8329616e3159ce74a2d354e6d3e85b537723f8fc by dgregor:

    [IRGen] Bind conditional requirements for witness table accessors.

    • edit: test/IRGen/conditional_conformances.swift
    • edit: lib/IRGen/GenProto.cpp
    • add: test/Inputs/conditional_conformance_recursive.swift

  • Commit 9b9923bd2e52a595a680d0b055fda51854a6df69 by dgregor:

    [IRGen] Bind conditional requirements in generic witness table

    • edit: lib/IRGen/GenProto.cpp
    • edit: test/Inputs/conditional_conformance_recursive.swift

  • Commit 7f17f44472955ce48d09849365067424a5c4ff34 by dgregor:

    [IRGen] Pass the appropriate conformance down for witness table access.

    • edit: lib/IRGen/GenProto.cpp

  • Commit 6b611a670bef3ed7da47f3e0324fad2f7635bff8 by gottesmm:

    [+0-all-args] Add a test that is a minimum implementation for for-each

    • add: test/SILGen/minimum_foreach.swift

  • Commit 85abdcd62de7197012abd7fead057f2283b03fa9 by github:

    Argparse "Overlay" Module (#12873)

    • add: utils/build_swift/argparse/__init__.py
    • edit: utils/build_swift/tests/expected_options.py
    • add: utils/build_swift/tests/argparse/test_parser.py
    • edit: utils/build_swift/driver_arguments.py
    • add: utils/build_swift/tests/argparse/test_actions.py
    • add: utils/build_swift/tests/argparse/test_types.py
    • add: utils/build_swift/argparse/actions.py
    • add: utils/build_swift/tests/argparse/__init__.py
    • add: utils/build_swift/tests/utils.py
    • add: validation-test/Python/build_swift.swift
    • add: utils/build_swift/argparse/types.py
    • edit: utils/build_swift/README.md
    • add: utils/build_swift/argparse/parser.py
    • edit: utils/build_swift/tests/test_driver_arguments.py

  • Commit 58f165a5624748117b5471ceb70468ff66110665 by spestov:

    AST: UnboundGenericTypes are not legal SIL types

    • edit: lib/AST/Type.cpp

  • Commit 47a3a66e528dcd5675d5acd7c7804f39fe637af9 by spestov:

    SILOptimizer: Kill off duplicated getAllSubclasses() algorithm

    • edit: include/swift/SILOptimizer/Utils/Devirtualize.h
    • edit: lib/SILOptimizer/Utils/Devirtualize.cpp
    • edit: lib/SILOptimizer/Transforms/SpeculativeDevirtualizer.cpp

  • Commit 1d6ec8e69e2616552665bf4a9ff13a53e5a783c1 by spestov:

    SILOptimizer: Fix incorrect check for unsupported generic case

    • edit: lib/SILOptimizer/Utils/Devirtualize.cpp
    • edit: lib/SILOptimizer/Transforms/SpeculativeDevirtualizer.cpp
    • add: test/SILOptimizer/devirt_speculative_nested.swift

  • Commit 2f0bc945fe9bf970a61eaf34b29d00107d43fac4 by spestov:

    SILOptimizer: Make a function static

    • edit: lib/SILOptimizer/Utils/Devirtualize.cpp

  • Commit 28d3e05d3768d1995fd4c949bde5216c05b2fa3c by spestov:

    IRGen: Remove obsolete FIXME

    • edit: lib/IRGen/GenMeta.cpp

  • Commit 91a7b5abbfacfe0200216161eb1d853689a751f4 by tstellar:

    Merging r318289:

    • add: test/DebugInfo/cross-cu-scope.ll
    • edit: lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp
    • edit: lib/CodeGen/AsmPrinter/DwarfDebug.h

  • Commit 138a40df8f33c6f5afcd402d3ab8276791465c3c by tstellar:

    Merging r313398:

    • edit: lib/IR/AutoUpgrade.cpp
    • edit: test/Bitcode/upgrade-module-flag.ll

  • Commit d07b802e93abfd9d33ef6dc4439058dfb8fb64c0 by tstellar:

    Merging r315086:

    • edit: lib/IR/AutoUpgrade.cpp
    • edit: include/llvm/IR/AutoUpgrade.h
    • add: test/Bitcode/upgrade-section-name.ll
    • edit: lib/Bitcode/Reader/BitcodeReader.cpp
    • edit: lib/AsmParser/LLParser.cpp

  • Commit f30c91881619bbedbdc70b3cb0ee9c90a67e51ee by tstellar:

    Merging r318788:

    • delete: test/CodeGen/AArch64/thread-pointer.ll
    • edit: lib/Target/AArch64/AArch64InstrInfo.td

  • Commit 7067b01d1fbef41752e7dfab064335040fb24140 by aprantl:

    Merging r318289:

    • edit: lib/CodeGen/AsmPrinter/DwarfDebug.h

  • Commit 3dd23183f2fa4f69f7425421d22aa3ee7a4f5826 by aprantl:

    Merging r315086:

    • edit: lib/IR/AutoUpgrade.cpp
    • edit: include/llvm/IR/AutoUpgrade.h
    • edit: lib/AsmParser/LLParser.cpp
    • edit: lib/Bitcode/Reader/BitcodeReader.cpp
    • add: test/Bitcode/upgrade-section-name.ll

  • Commit db7989ffcac6abc14554c7c83757e1caa7ffcea1 by aprantl:

    Merging r318788:

    • edit: lib/Target/AArch64/AArch64InstrInfo.td
    • delete: test/CodeGen/AArch64/thread-pointer.ll

  • Commit 97ab41bd7f4751f28022ff0458c1dda9766f40b5 by aschwaighofer:

    Inliner: Don't mark notail calls with the 'tail' attribute

    • edit: test/Transforms/Inline/inline-tail.ll
    • edit: lib/Transforms/Utils/InlineFunction.cpp

  • Commit 3e2da2092f539a3df1405460d6e40be0ba5af25b by enderby:

    Fix a crash in llvm-objdump when printing a bad x86_64 relocation in a

    • edit: tools/llvm-objdump/llvm-objdump.cpp
    • add: test/tools/llvm-objdump/X86/Inputs/macho-invalid-reloc-section-index
    • edit: test/tools/llvm-objdump/X86/malformed-machos.test

  • Commit 5d8a23e5a91ff48ca13867d0ee2f7f23d114bb47 by ahmed.bougacha:

    [globalisel][tablegen] Add support for multi-insn emission

    • add: test/CodeGen/AArch64/GlobalISel/select-bitcast-bigendian.mir
    • add: test/CodeGen/AArch64/GlobalISel/select-intrinsic-crypto-aesmc.mir
    • edit: test/TableGen/GlobalISelEmitter.td
    • edit: utils/TableGen/GlobalISelEmitter.cpp
    • edit: include/llvm/CodeGen/GlobalISel/InstructionSelector.h
    • edit: include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h

  • Commit dd026b3cbb70e770b31d44e81e7fc40f561a6096 by ahmed.bougacha:

    [globalisel][regbank] Warn about MIR ambiguities when register

    • edit: utils/TableGen/RegisterBankEmitter.cpp
    • edit: include/llvm/TableGen/Error.h
    • edit: lib/TableGen/Error.cpp

  • Commit 13f0c082d4e636c57faa1a02870fd0024dbad970 by ahmed.bougacha:

    [AArch64][RegisterBankInfo] Add FPR16 support in value mapping.

    • edit: lib/Target/AArch64/AArch64RegisterBankInfo.h
    • edit: lib/Target/AArch64/AArch64GenRegisterBankInfo.def
    • edit: lib/Target/AArch64/AArch64RegisterBankInfo.cpp

  • Commit 4e5f81eaad473f13bbb5031bc36475cf21cad4dc by ahmed.bougacha:

    [AArch64][RegisterBankInfo] Add mapping for G_FPEXT.

    • edit: lib/Target/AArch64/AArch64RegisterBankInfo.h
    • edit: lib/Target/AArch64/AArch64RegisterBankInfo.cpp
    • edit: lib/Target/AArch64/AArch64GenRegisterBankInfo.def
    • edit: test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir

  • Commit 89bea8d9cd368df93bea2850fea1d0981327f4ca by ahmed.bougacha:

    [ARM GlobalISel] Move the check for Thumb higher up

    • edit: lib/Target/ARM/ARMCallLowering.cpp

  • Commit 2cb57204b100129f31babd6ceb1c95d6d37d9f91 by ahmed.bougacha:

    [globalisel][tablegen] Skip src child predicates

    • edit: test/CodeGen/ARM/GlobalISel/arm-instruction-select-combos.mir
    • edit: utils/TableGen/GlobalISelEmitter.cpp

  • Commit f2787a544bcb41bfb7b7e1c9e4f9283cd67bc018 by ahmed.bougacha:

    [MIRPrinter] Use %subreg.xxx syntax for subregister index operands

    • edit: test/CodeGen/MIR/X86/subregister-index-operands.mir
    • edit: lib/CodeGen/MIRPrinter.cpp
    • edit: test/CodeGen/AArch64/GlobalISel/select-insert-extract.mir
    • edit: test/CodeGen/X86/GlobalISel/select-ext-x86-64.mir
    • edit: test/CodeGen/X86/GlobalISel/select-intrinsic-x86-flags-read-u32.mir
    • edit: test/CodeGen/AMDGPU/GlobalISel/inst-select-load-smrd.mir
    • edit: include/llvm/CodeGen/MachineInstr.h
    • edit: test/CodeGen/AMDGPU/detect-dead-lanes.mir
    • edit: test/CodeGen/AArch64/GlobalISel/select-int-ext.mir
    • edit: test/CodeGen/X86/GlobalISel/select-ext.mir
    • edit: test/CodeGen/AMDGPU/opt-sgpr-to-vgpr-copy.mir
    • edit: test/CodeGen/X86/GlobalISel/select-cmp.mir
    • edit: test/CodeGen/X86/GlobalISel/select-copy.mir

  • Commit 48fe102cdcd12f79ec41e98bb8cf3c34e6a96f29 by ahmed.bougacha:

    [GlobalISel] Enable legalizing non-power-of-2 sized types.

    • edit: lib/CodeGen/GlobalISel/LegalizerInfo.cpp
    • edit: lib/Target/ARM/ARMLegalizerInfo.cpp
    • edit: include/llvm/Support/LowLevelTypeImpl.h
    • edit: test/CodeGen/AArch64/GlobalISel/legalize-inserts.mir
    • edit: include/llvm/CodeGen/GlobalISel/LegalizerInfo.h
    • edit: lib/Target/AArch64/AArch64LegalizerInfo.cpp
    • edit: lib/Support/LowLevelType.cpp
    • edit: test/CodeGen/AArch64/GlobalISel/legalize-add.mir
    • edit: unittests/CodeGen/LowLevelTypeTest.cpp
    • edit: lib/CodeGen/GlobalISel/LegalizerHelper.cpp
    • edit: unittests/CodeGen/GlobalISel/LegalizerInfoTest.cpp
    • edit: test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll
    • edit: lib/Target/X86/X86LegalizerInfo.cpp
    • edit: test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir

  • Commit 2e053994f503c5363c4f04cc4ec60898b3afe358 by ahmed.bougacha:

    Silence C4715 warning from MSVC (NFC).

    • edit: lib/CodeGen/GlobalISel/LegalizerInfo.cpp

  • Commit 64faed0e9fccf39c9facd69d5430d67b7402bfd8 by ahmed.bougacha:

    Mark intentional fall-through with LLVM_FALLTHROUGH.

    • edit: lib/CodeGen/GlobalISel/LegalizerInfo.cpp

  • Commit cda09642cfda037748a5a2ad95ee652e27296a58 by ahmed.bougacha:

    [globalisel][tablegen] Import signextload and zeroextload.

    • edit: utils/TableGen/CodeGenDAGPatterns.cpp
    • edit: utils/TableGen/CodeGenDAGPatterns.h
    • edit: lib/CodeGen/GlobalISel/InstructionSelector.cpp
    • edit: test/TableGen/GlobalISelEmitter.td
    • edit: test/CodeGen/AArch64/GlobalISel/select-load.mir
    • edit: utils/TableGen/GlobalISelEmitter.cpp
    • edit: include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h
    • edit: include/llvm/CodeGen/GlobalISel/InstructionSelector.h

  • Commit e6d1e5b541f284b4dab9e6ef8e2dd99255807594 by ahmed.bougacha:

    [ARM GlobalISel] Update legalizer test

    • edit: test/CodeGen/ARM/GlobalISel/arm-legalizer.mir

  • Commit 36932f9189738a9769ff3d38d00697a1b33dc91e by ahmed.bougacha:

    [globalisel][tablegen] Add support for extload.

    • edit: utils/TableGen/GlobalISelEmitter.cpp
    • edit: test/CodeGen/AArch64/GlobalISel/select-load.mir

  • Commit 7a90780e4becd8cd34a9ead7d3dce44777efcdef by ahmed.bougacha:

    [ARM GlobalISel] Remove C++ code for G_CONSTANT

    • edit: test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir
    • edit: lib/Target/ARM/ARMInstructionSelector.cpp
    • edit: test/CodeGen/ARM/GlobalISel/arm-isel-divmod.ll

  • Commit ec0db39c108e574c68d198267d422863970ed4b4 by ahmed.bougacha:

    [GISel]: Rework legalization algorithm for better elimination of

    • edit: test/CodeGen/AMDGPU/GlobalISel/legalize-select.mir
    • edit: test/CodeGen/AMDGPU/GlobalISel/legalize-or.mir
    • edit: test/CodeGen/X86/GlobalISel/legalize-constant.mir
    • edit: test/CodeGen/X86/GlobalISel/legalize-add-v128.mir
    • edit: lib/CodeGen/GlobalISel/Legalizer.cpp
    • edit: test/CodeGen/X86/GlobalISel/legalize-phi.mir
    • edit: test/CodeGen/AArch64/GlobalISel/legalize-xor.mir
    • edit: test/CodeGen/AArch64/GlobalISel/legalize-vaarg.mir
    • edit: test/CodeGen/AMDGPU/GlobalISel/legalize-bitcast.mir
    • edit: test/CodeGen/X86/GlobalISel/legalize-sub-v128.mir
    • edit: test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir
    • edit: test/CodeGen/X86/GlobalISel/legalize-memop-scalar.mir
    • edit: test/CodeGen/X86/GlobalISel/and-scalar.ll
    • edit: test/CodeGen/AArch64/GlobalISel/legalize-phi.mir
    • edit: test/CodeGen/ARM/GlobalISel/arm-isel.ll
    • edit: test/CodeGen/AArch64/GlobalISel/legalize-ext.mir
    • edit: test/CodeGen/AArch64/GlobalISel/legalize-extracts.mir
    • edit: test/CodeGen/AArch64/GlobalISel/legalize-fptoi.mir
    • delete: include/llvm/CodeGen/GlobalISel/LegalizerCombiner.h
    • edit: test/CodeGen/AArch64/GlobalISel/legalize-sub.mir
    • edit: test/CodeGen/X86/GlobalISel/legalize-add-v256.mir
    • edit: test/CodeGen/X86/GlobalISel/legalize-and-scalar.mir
    • edit: test/CodeGen/AMDGPU/GlobalISel/legalize-fmul.mir
    • edit: test/CodeGen/X86/GlobalISel/add-scalar.ll
    • add: include/llvm/CodeGen/GlobalISel/GISelWorkList.h
    • edit: test/CodeGen/AArch64/GlobalISel/legalize-nonpowerof2eltsvec.mir
    • edit: test/CodeGen/X86/GlobalISel/sub-scalar.ll
    • edit: test/CodeGen/X86/GlobalISel/legalize-sub.mir
    • edit: test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll
    • edit: test/CodeGen/AArch64/GlobalISel/legalize-itofp.mir
    • edit: test/CodeGen/X86/GlobalISel/ext.ll
    • edit: test/CodeGen/X86/GlobalISel/legalize-ext-x86-64.mir
    • edit: test/CodeGen/X86/GlobalISel/xor-scalar.ll
    • edit: test/CodeGen/AArch64/GlobalISel/legalize-undef.mir
    • edit: test/CodeGen/AMDGPU/GlobalISel/legalize-shl.mir
    • edit: test/CodeGen/X86/GlobalISel/legalize-ext.mir
    • edit: test/CodeGen/X86/GlobalISel/legalize-mul-scalar.mir
    • edit: test/CodeGen/X86/GlobalISel/legalize-sub-v512.mir
    • edit: test/CodeGen/AArch64/GlobalISel/legalize-pow.mir
    • edit: test/CodeGen/X86/GlobalISel/legalize-add-v512.mir
    • edit: test/CodeGen/AMDGPU/GlobalISel/legalize-constant.mir
    • edit: test/CodeGen/AArch64/GlobalISel/legalize-add.mir
    • edit: test/CodeGen/X86/GlobalISel/legalize-undef.mir
    • add: include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h
    • edit: test/CodeGen/AArch64/GlobalISel/legalize-simple.mir
    • edit: test/CodeGen/AArch64/GlobalISel/legalize-fcmp.mir
    • edit: test/CodeGen/AArch64/GlobalISel/legalize-mul.mir
    • edit: test/CodeGen/X86/GlobalISel/legalize-xor-scalar.mir
    • edit: test/CodeGen/AArch64/GlobalISel/legalize-combines.mir
    • edit: test/CodeGen/AArch64/GlobalISel/legalize-rem.mir
    • edit: test/CodeGen/X86/GlobalISel/legalize-or-scalar.mir
    • edit: test/CodeGen/X86/GlobalISel/legalize-trunc.mir
    • edit: test/CodeGen/AMDGPU/GlobalISel/legalize-and.mir
    • edit: test/CodeGen/X86/GlobalISel/legalize-add.mir
    • edit: test/CodeGen/X86/GlobalISel/or-scalar.ll
    • edit: test/CodeGen/AMDGPU/GlobalISel/legalize-add.mir
    • edit: test/CodeGen/AMDGPU/GlobalISel/legalize-icmp.mir
    • edit: test/CodeGen/AArch64/GlobalISel/legalize-constant.mir
    • edit: test/CodeGen/AArch64/GlobalISel/legalize-div.mir
    • edit: test/CodeGen/AArch64/GlobalISel/legalize-shift.mir
    • edit: test/CodeGen/AArch64/GlobalISel/legalize-and.mir
    • edit: test/CodeGen/AMDGPU/GlobalISel/legalize-fadd.mir
    • edit: test/CodeGen/AArch64/GlobalISel/legalize-cmp.mir
    • edit: test/CodeGen/AArch64/GlobalISel/legalize-inserts.mir
    • edit: test/CodeGen/AArch64/GlobalISel/legalize-or.mir
    • edit: test/CodeGen/X86/GlobalISel/legalize-gep.mir
    • edit: test/CodeGen/X86/GlobalISel/legalize-sub-v256.mir
    • edit: test/CodeGen/ARM/GlobalISel/arm-legalize-divmod.mir
    • edit: test/CodeGen/ARM/GlobalISel/arm-legalize-fp.mir
    • edit: test/CodeGen/X86/GlobalISel/x86_64-fallback.ll

  • Commit 2e7a564987682a49b6345c764b443ea174bbebd7 by ahmed.bougacha:

    GISelWorkList.h: Fix -fmodules build in rL318210.

    • edit: include/llvm/CodeGen/GlobalISel/GISelWorkList.h

  • Commit 2d078ebe72d8ba47b16fc64e16d2f017f097ef76 by ahmed.bougacha:

    [GISel][NFC]: Move getOpcodeDef from the LegalizationArtifactCombiner

    • edit: include/llvm/CodeGen/GlobalISel/Utils.h
    • edit: include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h
    • edit: lib/CodeGen/GlobalISel/Utils.cpp

  • Commit c8a487cb68597aecd38c0e4e419be67bc5f28049 by ahmed.bougacha:

    [globalisel][tablegen] Generate rule coverage and use it to identify

    • edit: include/llvm/CodeGen/GlobalISel/InstructionSelector.h
    • edit: test/TableGen/GlobalISelEmitter.td
    • add: include/llvm/Support/CodeGenCoverage.h
    • add: utils/llvm-gisel-cov.py
    • edit: lib/Target/ARM/ARMInstructionSelector.cpp
    • edit: lib/Target/X86/X86InstructionSelector.cpp
    • edit: lib/Target/AArch64/AArch64InstructionSelector.cpp
    • edit: lib/CodeGen/GlobalISel/InstructionSelect.cpp
    • edit: lib/Support/CMakeLists.txt
    • edit: utils/TableGen/GlobalISelEmitter.cpp
    • edit: lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
    • edit: include/llvm/Config/config.h.cmake
    • edit: include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h
    • edit: lib/Target/AMDGPU/AMDGPUInstructionSelector.h
    • edit: cmake/modules/TableGen.cmake
    • edit: CMakeLists.txt
    • add: lib/Support/CodeGenCoverage.cpp

  • Commit e9f66f0da7284100297000195e8d3d249dc1eda4 by ahmed.bougacha:

    [ARM GlobalISel] Add tests for REVSH patterns. NFC

    • edit: test/CodeGen/ARM/GlobalISel/arm-instruction-select-combos.mir

  • Commit c1916c47748fc65d755b4e8de406fe27dba7c0cb by ahmed.bougacha:

    [ARM GlobalISel] Add tests for BIC. NFC

    • edit: test/CodeGen/ARM/GlobalISel/arm-instruction-select-combos.mir

  • Commit 45e3da6801c133697fd5a5d343a041254dac5473 by ahmed.bougacha:

    [GISel]: DCE copy instructions during legalization

    • edit: include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h
    • edit: test/CodeGen/AArch64/GlobalISel/legalize-simple.mir

  • Commit aeca4adabc86ecf9be933fc7e59f3ea7893934e3 by ahmed.bougacha:

    [globalisel][tablegen] Generalize pointer-type inference by introducing

    • edit: utils/TableGen/CodeGenInstruction.h
    • edit: include/llvm/Target/GenericOpcodes.td
    • edit: include/llvm/Target/Target.td
    • edit: utils/TableGen/GlobalISelEmitter.cpp
    • edit: utils/TableGen/CodeGenInstruction.cpp

  • Commit 516ce18a59e6a1ed9908cde9c2ac795cd1734599 by ahmed.bougacha:

    [AArch64][RegisterBankInfo] Teach instruction mapping about gpr32 ->

    • edit: test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir
    • edit: lib/Target/AArch64/AArch64GenRegisterBankInfo.def

  • Commit 82524871bca16b38f011342d2f37d07ab5b8448e by ahmed.bougacha:

    [RegisterBankInfo] Relax the assert of having matching type sizes on

    • edit: lib/CodeGen/GlobalISel/RegisterBankInfo.cpp
    • edit: test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir

  • Commit 36c54f92fe2a50d4dc6395e41620c522e7ccd0d8 by ahmed.bougacha:

    [AArch64] Map G_STORE on FPR when the source comes from a FPR copy

    • edit: lib/Target/AArch64/AArch64RegisterBankInfo.cpp
    • edit: test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir

  • Commit dd9153b752f02a0a5cd90fecb59225934d31623d by ahmed.bougacha:

    [AArch64] Map G_LOAD on FPR when the definition goes to a copy to FPR

    • edit: lib/Target/AArch64/AArch64RegisterBankInfo.cpp
    • edit: test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir

  • Commit 329a0f30b1edb72483fb96d715d45f537cbc0153 by ahmed.bougacha:

    [ARM GlobalISel] Clean up binary operator tests. NFC

    • edit: test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir

  • Commit 155a0cf0278e50e75861b5f9f4ffd4cba6c2aaa8 by ahmed.bougacha:

    [ARM GlobalISel] Add test for RSBri. NFC

    • edit: test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir

  • Commit f889bafb35d55b174ea0915f10aad112f5a184e7 by ahmed.bougacha:

    [ARM GlobalISel] Add comment for r318398. NFC.

    • edit: test/CodeGen/ARM/GlobalISel/arm-instruction-select-combos.mir

  • Commit bf25b5a9a1c19bacd8c47608392d12aea838a864 by ahmed.bougacha:

    [ARM GlobalISel] Support G_FMUL for s32 and s64

    • edit: test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir
    • edit: test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir
    • edit: lib/CodeGen/GlobalISel/LegalizerHelper.cpp
    • edit: lib/Target/ARM/ARMRegisterBankInfo.cpp
    • edit: test/CodeGen/ARM/GlobalISel/arm-legalize-fp.mir
    • edit: lib/Target/ARM/ARMLegalizerInfo.cpp

  • Commit 8e66248bbe89032e23695df95f9fa5ad83ef79a1 by ahmed.bougacha:

    [ARM GlobalISel] Support G_FDIV for s32 and s64

    • edit: lib/Target/ARM/ARMLegalizerInfo.cpp
    • edit: lib/Target/ARM/ARMRegisterBankInfo.cpp
    • edit: test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir
    • edit: test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir
    • edit: lib/CodeGen/GlobalISel/LegalizerHelper.cpp
    • edit: test/CodeGen/ARM/GlobalISel/arm-legalize-fp.mir

  • Commit d6f626ab243cadc63cc8f2d18daaab1873effd0d by ahmed.bougacha:

    MIRParser: Avoid reading uninitialized memory on generic vregs

    • edit: lib/CodeGen/MIRParser/MIRParser.cpp

  • Commit c8e559fd097469e169c92e748292b9edb96c1dcb by ahmed.bougacha:

    Add backend name to Target to enable runtime info to be fed back into

    • edit: lib/Support/TargetRegistry.cpp
    • edit: lib/Target/PowerPC/TargetInfo/PowerPCTargetInfo.cpp
    • edit: lib/Target/AArch64/TargetInfo/AArch64TargetInfo.cpp
    • edit: lib/Target/XCore/TargetInfo/XCoreTargetInfo.cpp
    • edit: lib/Target/ARM/TargetInfo/ARMTargetInfo.cpp
    • edit: lib/Target/Hexagon/TargetInfo/HexagonTargetInfo.cpp
    • edit: lib/Target/X86/TargetInfo/X86TargetInfo.cpp
    • edit: lib/Target/AMDGPU/TargetInfo/AMDGPUTargetInfo.cpp
    • edit: lib/Target/SystemZ/TargetInfo/SystemZTargetInfo.cpp
    • edit: lib/Target/Sparc/TargetInfo/SparcTargetInfo.cpp
    • edit: lib/Target/BPF/TargetInfo/BPFTargetInfo.cpp
    • edit: lib/Target/Mips/TargetInfo/MipsTargetInfo.cpp
    • edit: lib/Target/Lanai/TargetInfo/LanaiTargetInfo.cpp
    • edit: include/llvm/Support/TargetRegistry.h
    • edit: lib/Target/MSP430/TargetInfo/MSP430TargetInfo.cpp
    • edit: lib/Target/NVPTX/TargetInfo/NVPTXTargetInfo.cpp

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