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To all,
I just found the table I was looking for. I attached it in my mail, for
your informations.
Stephane.
______________________________ Forward Header
__________________________________
Subject: A different device detection proposal
Author: hlandis ([EMAIL PROTECTED]) at internet
Date: 08/06/00 17:52
This email contains two items: first, I have updated my reset
signature table to show Larry Barras' proposal, second, is my
proposal for doing much the same thing. It is important to note
that my proposal, unlike Larry's, should not require hardware
changes in the device interface chip.
--- First, Larry Barras ---
Based on the proposal from Larry Barras I have updated my "device
detection table". This table shows Larry's proposed change on
lines a' and d'.
This table shows the signature values in SC, SN, CL and CH and
the status in ST at two times. The first status is right after
device 0 sets BSY=0. Now assume that if there are two ATA
devices, that those devices have basically the same spin up
times. Lets assume that is 10 seconds. So the table shows the
status a second time, labelled ST2, after the ATA spin up time.
So the ST and ST2 values are read by the host at least 10 seconds
apart. And be careful, issuing a command or a Soft Reset while
an ATA device has status of 00 does not change the state of DRDY.
'RDY' means the ATA device has set DRDY=1 so it probably has
status of 40 or 50.
'none*' means the register values are being supplied by device 0.
This proposal requires hardware changes in the device interface
chip.
# dev0 SC SN CL CH ST ST2 dev1 SC SN CL CH ST ST2
a ata 01 01 00 00 00 RDY none* 01 01 00 00 00 00
a' ata 01 01 00 00 00 RDY none* 00 00 00 00 00 00
b ata 01 01 00 00 00 RDY ata 01 01 00 00 00 RDY
c ata 01 01 00 00 00 RDY atapi 01 01 14 eb 00 00
d atapi 01 01 14 eb 00 00 none* 01 01 14 eb 00 00
d' atapi 01 01 14 eb 00 00 none* 00 00 14 eb 00 00
e atapi 01 01 14 eb 00 00 ata 01 01 00 00 00 RDY
f atapi 01 01 14 eb 00 00 atapi 01 01 14 eb 00 00
g none ?? ?? ?? ?? none ?? ?? ?? ?? ?? ??
h none ?? ?? ?? ?? ata 01 01 00 00 00 RDY
i none ?? ?? ?? ?? atapi 01 01 14 eb 00 00
--- Second, Hale Landis ---
Here is my (old) proposal (again, again and again, good grief
this proposal is something like four years old!).
The basic problem to be solved: What can be done to make the
first status indicate if device 1 is present?
Both ATA and ATAPI devices set the SC and SN number registers to
the value 01. My suggestion, first made many years ago, is that
device 0 sets SC to 02 if there is a device 1 and to 03 if there
is no device 1. The old 01 code would mean that device 0 does not
support reporting the state of device 1. This should be a simple
firmware change in the H/W reset, S/W reset and EXEC DEV DIAG
processing, that is, override the hardware defaulted 01 value in
the SC register before setting BSY=0. And in the future it could
even be done by the device's hardware.
This table shows the signature values in SC, SN, CL and CH and
the status in ST at two times. The first status is right after
device 0 sets BSY=0. Now assume that if there are two ATA
devices, that those devices have basically the same spin up
times. Lets assume that is 10 seconds. So the table shows the
status a second time, labelled ST2, after the ATA spin up time.
So the ST and ST2 values are read by the host at least 10 seconds
apart. And be careful, issuing a command or a Soft Reset while
an ATA device has status of 00 does not change the state of DRDY.
'RDY' means the ATA device has set DRDY=1 so it probably has
status of 40 or 50.
'none*' means the register values are being supplied by device 0.
The important thing for today's devices is that is can be done
without hardware changes.
The proposed change is shown on lines a' and d'.
# dev0 SC SN CL CH ST ST2 dev1 SC SN CL CH ST ST2
a ata 01 01 00 00 00 RDY none* 01 01 00 00 00 00
a' ata 03 01 00 00 00 RDY none* 03 01 00 00 00 00
b ata 02 01 00 00 00 RDY ata 01 01 00 00 00 RDY
c ata 02 01 00 00 00 RDY atapi 01 01 14 eb 00 00
d atapi 01 01 14 eb 00 00 none* 01 01 14 eb 00 00
d' atapi 03 01 14 eb 00 00 none* 03 01 14 eb 00 00
e atapi 02 01 14 eb 00 00 ata 01 01 00 00 00 RDY
f atapi 02 01 14 eb 00 00 atapi 01 01 14 eb 00 00
g none ?? ?? ?? ?? none ?? ?? ?? ?? ?? ??
h none ?? ?? ?? ?? ata 01 01 00 00 00 RDY
i none ?? ?? ?? ?? atapi 01 01 14 eb 00 00
--- Summary ---
Larry's proposal, which is very similar to the old SFF-8038
method, requires hardware changes so that device 0 forces 00 on
the data bus when the host reads device 1's registers. This is
one of the many reasons the SFF-8038 method was flawed and not
popular with many device interface chip designers.
My (very old proposal) does not require this hardware change. My
proposal can most likely be implemented in firmware by having the
device firmware change the contents of the SC register before
setting BSY=0. Virtually all ATA/ATAPI interface chips set the
SC register to 01 in hardware but this can be overwritten by the
firmware.
+++ Hale Landis --- Niwot, CO USA --- www.ata-atapi.com +++
+++ [EMAIL PROTECTED] --- [EMAIL PROTECTED] +++
CC: hlandis / internet
DDT1=RFC-822; [EMAIL PROTECTED];
TO: t13 / internet
DDT1=RFC-822; [EMAIL PROTECTED];
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