** This is the quasi-official and semi-temporary T13 email list server. ** Hi I have wrote a program to carry out UDMA transfer on an addon PCI-IDE card. Here is the program flow: 1.prepare a PRD list : use memset() to set a region of the memory to certain value ,such as 0xff. Then write the start address of the PRD list into the PRD register of the PCI-IDE chip, as described in SF8038. 2.Clear channel interrupt bit of the PCI-IDE chip 3.Clear DMA status bits of the PCI-IDE chip 4.Set Read/Write contro,here I choose the DMA Read function 5.Config the hard disk: select the drive, set the LBA address to specific registers,etc. 6.Issue DMA transfer command to the drive 7.Wait for a while to ensure the disk is ready. 8.Config the PCI-IDE chip, 9.Start the bus master function by writing start bit to the BMCR 10.Wait for interrupt to indicate transfer completion. 11.disable/stop the dma channel and verify command success after step10 I have put several breakpoints in the program to trail the progress. A unknown prolem occured at step 10, where the status register of the disk was read as 0x58, and bus master status register was read as 0x21 program halted here waiting for the interrupt. Unfortunately , it seems that there must be something wrong in the chip setting that the interrupt has never come. Steps before 10 have not introduce any error to disk and chip. So I am confused about this. Is it caused by the PRD address? Is there any flaw in the program flow.Or some other kind of settings? Thanks -- If you have any questions or wish to unsubscribe send a message to Hale Landis, [EMAIL PROTECTED] To post to this list server send your message to [EMAIL PROTECTED] For questions concerning Thistle Grove Industries or TGI's list services please send email to [EMAIL PROTECTED]
