On Fri, Mar 20, 2015 at 07:34:35AM -0400, R. Russell Reiter wrote: > You might find this interesting. It is Yale U announcing VLIW reasoning in > the 80's. More work with less iron and from my perspective, instructions > ordered at compile time makes for fewer clocking issues.
Yes it does. Hence why VLIW is working great in DSPs where you know exactly what you will be doing all the time at compile time. In general purpose software on the other hand you don't know at compile time, and the compiler can not generate efficient code for VLIW and ends up rarely generating more than one instruction per VLIW, while a more complex CPU design (like most of the ones people actually buy and use) that do run time instruction reordering are able to actually use multiple execution units per clock cycle. So yes VLIW is more efficient if you order the instructions at compile time. Too bad in reality that has turned out to be impossible in the general case. Makes wonderful DSP/GPU/other stream processing chips though. -- Len Sorensen --- Talk Mailing List [email protected] http://gtalug.org/mailman/listinfo/talk
