On Thu, 2020-01-23 at 14:41 -0300, Martin Galvan wrote: > Hi all, > > I just ran txt-stat on a system which has an IceLake CPU and a 495 > Series PCH, and am seeing the following output: > > Intel(r) TXT Configuration Registers: > STS: 0x00000003 > senter_done: TRUE > sexit_done: TRUE > mem_config_lock: FALSE > private_open: FALSE > locality_1_open: FALSE > locality_2_open: FALSE > ESTS: 0x00 > txt_reset: FALSE > E2STS: 0x0000000000000004 > secrets: FALSE > ERRORCODE: 0x00000000 > DIDVID: 0x00000001b00a8086 > vendor_id: 0x8086 > device_id: 0xb00a > revision_id: 0x1 > FSBIF: 0xffffffffffffffff > QPIIF: 0x000000009d003000 > SINIT.BASE: 0x00000000 > SINIT.SIZE: 0B (0x0) > HEAP.BASE: 0x00000000 > HEAP.SIZE: 0B (0x0) > DPR: 0x0000000000000000 > lock: FALSE > top: 0x00000000 > size: 0MB (0B) > PUBLIC.KEY: > 87 9a 8f 9c bf 9e 3d 1d 12 dc 9a d7 6d de 34 e6 > aa 40 36 64 c7 39 db 34 7b 85 8f 0b e0 33 ae 3a > > *********************************************************** > TXT measured launch: TRUE > secrets flag set: FALSE > *********************************************************** > unable to find TBOOT log > > I'm seeing that the SENTER.DONE.STS and SEXIT.DONE.STS bits are both > set. If I understood right, this doesn't make sense since they signal > whether all the threads are running the code within the MLE or not > (I'm not running an MLE here). In addition, the DID reported by > TXT.DIDVID doesn't match that of my PCH (which is 0x3482). Am I doing > something wrong here? >
Hi Martin I see that your SINIT.BASE and HEAP.BASE registers have all zeros, did you enable TXT in BIOS? I guess that txt-stat may not check if TXT is enabled before reading TXT related registers, that's why you can have strange, random values. Thanks, Lukasz _______________________________________________ tboot-devel mailing list tboot-devel@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/tboot-devel
