>> There are two interesting things here: the timestamps in the file do >> not warp backwards by almost two seconds - but they do warp >> backwards, by 3353 ns. > Try a different time counter. See kern.timecounter.
kern.timecounter.choice = clockinterrupt(q=0, f=100 Hz) TSC(q=-100, f=1795636350 Hz) ACPI-Fast(q=1000, f=3579545 Hz) i8254(q=100, f=1193182 Hz) dummy(q=-1000000, f=1000000 Hz) kern.timecounter.hardware = ACPI-Fast kern.timecounter.timestepwarnings = 0 I switched to TSC and got the same syndrome (well, as far as kdump output goes; I didn't dig into ktrace.out). Switching to clockinterrupt made the syndrome go away, but all the timestamp deltas printed by kdump -R were zero (there probably were a very few that weren't, but I didn't see any of them in a quick eyeball skim). > Is this UP or MP? MP. cpu0 at mainbus0: apid 0 (boot processor) cpu0: Intel Core 2 (Merom) (686-class), 1795.62 MHz, id 0x6fd cpu0: features bfebfbff<FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR> cpu0: features bfebfbff<PGE,MCA,CMOV,PAT,PSE36,CFLUSH,DS,ACPI,MMX> cpu0: features bfebfbff<FXSR,SSE,SSE2,SS,HTT,TM,SBF> cpu0: features2 e3bd<SSE3,MONITOR,DS-CPL,VMX,EST,TM2,xTPR> cpu0: "Intel(R) Core(TM)2 Duo CPU T7100 @ 1.80GHz" cpu0: I-cache 32 KB 64B/line 8-way, D-cache 32 KB 64B/line 8-way cpu0: L2 cache 2 MB 64B/line 8-way cpu0: using thermal monitor 1 cpu0: Enhanced SpeedStep (1420 mV) 2000 MHz cpu0: unknown Enhanced SpeedStep CPU. cpu0: using only highest and lowest power states. cpu0: Enhanced SpeedStep frequencies available (MHz): 2000 1200 cpu0: calibrating local timer cpu0: apic clock running at 199 MHz cpu0: 64 page colors cpu1 at mainbus0: apid 1 (application processor) cpu1: starting cpu1: Intel Core 2 (Merom) (686-class), 1795.43 MHz, id 0x6fd cpu1: features bfebfbff<FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR> cpu1: features bfebfbff<PGE,MCA,CMOV,PAT,PSE36,CFLUSH,DS,ACPI,MMX> cpu1: features bfebfbff<FXSR,SSE,SSE2,SS,HTT,TM,SBF> cpu1: features2 e3bd<SSE3,MONITOR,DS-CPL,VMX,EST,TM2,xTPR> cpu1: "Intel(R) Core(TM)2 Duo CPU T7100 @ 1.80GHz" cpu1: I-cache 32 KB 64B/line 8-way, D-cache 32 KB 64B/line 8-way cpu1: L2 cache 2 MB 64B/line 8-way cpu1: using thermal monitor 1 I did consider the possibility that MP was relevant, but it strikes me as highly unlikely that it would migrate between processors exactly there every time (and, apparently, _only_ there). Is it likely enough that it's something else tied to MPness that it's worth trying a test under a UP kernel? /~\ The ASCII Mouse \ / Ribbon Campaign X Against HTML mo...@rodents-montreal.org / \ Email! 7D C8 61 52 5D E7 2D 39 4E F1 31 3E E8 B3 27 4B
