On Fri, Sep 30, 2011 at 03:36:14PM +0900, Masao Uebayashi wrote: > > - is there any architecture which allows MP with different cache-line sizes?
At a guess, this can probably happen on an SGI Challenge (a real Challenge, that is, a DM, L, or XL, not a "Challenge S"). It is possible it can also happen on supported configurations of the successor CrayLink-based platforms (Origin 200/2xxx/3x0/3xxx) even including Altix though I doubt such configurations were ever supported even by SGI. Do we care? Probably not. But Challenge and Origin are nice examples of how weird big MP platforms can be and still get good performance through excellent kernel implementation (Origin is very, very NUMA and the Irix kernel deals with this very very well) so sometimes it might be worth thinking about what we'd need to do to run on such platforms with acceptable performance. It's unfortunate that even after excising most of the AT&T code -- maybe all? -- SGI never really opened up any of the Irix sources except XFS. Thor
