> Or the performance are constrained by something unrelated. In the blog > post cited above, the poster acheived more than 5 Gb/s before touching > MMRBC, while I am stuck at 2,7 GB/s. Any new idea welcome.
The blog post refers to PCI-X, I'm more familiar with PCIe, but the concepts are similar. There are several possibilities, all revolving about differences between the blog poster's base system and yorus. 1) the test case is using a platform that has better PCI performance (in the PCIe world this could be: Gen3 versus Gen2 support in the slot being used; more lanes in the slot being used) 2) the test case has a root complex with a PCI controller with better performance than the one in your system; 3) the test case system has a different PCI configuration, in particular different bridging. For example, a PCI bridge or switch on your platform can change basic capabilities compared to the reference. 4) related to 3: one of the bridges on your system (between ixg and root complex) is not configured for 4K reads, and so the setting on the ixg board won't help [whereas this wasn't the case on the blog system]. 5) related to 4: one of the bridges in your system (between ixg and root complex) is not capable of 4K reads... (see 4). And of course you have to consider: 6) the writer has something else different than you have, for example silicon rev, BIOS, PCI-X where you have PCIe, etc. 7) the problem is completely unrelated to PCIe. You're in a tough situation, experimentally, because you can't take a working (5 Gbps) system and directly compare to the non-working (2.7 Gbps) situation. --Terry
