Hi, Emmanuel.

On 2014/09/01 11:10, Emmanuel Dreyfus wrote:
> Terry Moore <t...@mcci.com> wrote:
> 
>> Since you did a dword read, the extra 0x9.... is the device status register.
>> This makes me suspicious as the device status register is claiming that you
>> have "unsupported request detected)" [bit 3] and "correctable error
>> detected" [bit 0].  Further, this register is RW1C for all these bits -- so
>> when you write 94810, it should have cleared the 9 (so a subsequent read
>> should have returned 4810).
>>
>> Please check.
> 
> You are right;
> # pcictl /dev/pci5 read -d 0 -f 1 0xa8
> 00092810
> # pcictl /dev/pci5 write -d 0 -f 1 0xa8 0x00094810
> # pcictl /dev/pci5 read -d 0 -f 1 0xa8
> 00004810
> 
>> Might be good to post a "pcictl dump" of your device, just to expose all the
>> details.
> 
> It explicitely says 2.5 Gb/s x 8 lanes
> 
> # pcictl /dev/pci5 dump -d0 -f 1
> PCI configuration registers:
>    Common header:
>      0x00: 0x10fb8086 0x00100107 0x02000001 0x00800010
> 
>      Vendor Name: Intel (0x8086)
>      Device Name: 82599 (SFI/SFP+) 10 GbE Controller (0x10fb)
>      Command register: 0x0107
>        I/O space accesses: on
>        Memory space accesses: on
>        Bus mastering: on
>        Special cycles: off
>        MWI transactions: off
>        Palette snooping: off
>        Parity error checking: off
>        Address/data stepping: off
>        System error (SERR): on
>        Fast back-to-back transactions: off
>        Interrupt disable: off
>      Status register: 0x0010
>        Interrupt status: inactive
>        Capability List support: on
>        66 MHz capable: off
>        User Definable Features (UDF) support: off
>        Fast back-to-back capable: off
>        Data parity error detected: off
>        DEVSEL timing: fast (0x0)
>        Slave signaled Target Abort: off
>        Master received Target Abort: off
>        Master received Master Abort: off
>        Asserted System Error (SERR): off
>        Parity error detected: off
>      Class Name: network (0x02)
>      Subclass Name: ethernet (0x00)
>      Interface: 0x00
>      Revision ID: 0x01
>      BIST: 0x00
>      Header Type: 0x00+multifunction (0x80)
>      Latency Timer: 0x00
>      Cache Line Size: 0x10
> 
>    Type 0 ("normal" device) header:
>      0x10: 0xdfe8000c 0x00000000 0x0000bc01 0x00000000
>      0x20: 0xdfe7c00c 0x00000000 0x00000000 0x00038086
>      0x30: 0x00000000 0x00000040 0x00000000 0x00000209
> 
>      Base address register at 0x10
>        type: 64-bit prefetchable memory
>        base: 0x00000000dfe80000, not sized
>      Base address register at 0x18
>        type: i/o
>        base: 0x0000bc00, not sized
>      Base address register at 0x1c
>        not implemented(?)
>      Base address register at 0x20
>        type: 64-bit prefetchable memory
>        base: 0x00000000dfe7c000, not sized
>      Cardbus CIS Pointer: 0x00000000
>      Subsystem vendor ID: 0x8086
>      Subsystem ID: 0x0003
>      Expansion ROM Base Address: 0x00000000
>      Capability list pointer: 0x40
>      Reserved @ 0x38: 0x00000000
>      Maximum Latency: 0x00
>      Minimum Grant: 0x00
>      Interrupt pin: 0x02 (pin B)
>      Interrupt line: 0x09
> 
>    Capability register at 0x40
>      type: 0x01 (Power Management, rev. 1.0)
>    Capability register at 0x50
>      type: 0x05 (MSI)
>    Capability register at 0x70
>      type: 0x11 (MSI-X)
>    Capability register at 0xa0
>      type: 0x10 (PCI Express)
> 
>    PCI Message Signaled Interrupt
>      Message Control register: 0x0180
>        MSI Enabled: no
>        Multiple Message Capable: no (1 vector)
>        Multiple Message Enabled: off (1 vector)
>        64 Bit Address Capable: yes
>        Per-Vector Masking Capable: yes
>      Message Address (lower) register: 0x00000000
>      Message Address (upper) register: 0x00000000
>      Message Data register: 0x00000000
>      Vector Mask register: 0x00000000
>      Vector Pending register: 0x00000000
> 
>    PCI Power Management Capabilities Register
>      Capabilities register: 0x4823
>        Version: 1.2
>        PME# clock: off
>        Device specific initialization: on
>        3.3V auxiliary current: self-powered
>        D1 power management state support: off
>        D2 power management state support: off
>        PME# support: 0x09
>      Control/status register: 0x2000
>        Power state: D0
>        PCI Express reserved: off
>        No soft reset: off
>        PME# assertion disabled
>        PME# status: off
> 
>    PCI Express Capabilities Register
>      Capability version: 2
>      Device type: PCI Express Endpoint device
>      Interrupt Message Number: 0
>      Link Capabilities Register: 0x00027482
>        Maximum Link Speed: unknown 2 value
>        Maximum Link Width: x8 lanes
>        Port Number: 0
>      Link Status Register: 0x1081
>        Negotiated Link Speed: 2.5Gb/s
                                    *

Which Version of NetBSD are you using?

 I committed some changes fixing Gb/s to GT/s in pci_sbur.c.
It was in April, 2013. I suspect you are using netbsd-6, or
you are using -current with old /usr/lib/libpci.so.


>        Negotiated Link Width: x8 lanes
> 
>    Device-dependent header:
>      0x40: 0x48235001 0x2b002000 0x00000000 0x00000000
>      0x50: 0x01807005 0x00000000 0x00000000 0x00000000
>      0x60: 0x00000000 0x00000000 0x00000000 0x00000000
>      0x70: 0x003fa011 0x00000004 0x00002004 0x00000000
>      0x80: 0x00000000 0x00000000 0x00000000 0x00000000
>      0x90: 0x00000000 0x00000000 0x00000000 0x00000000
>      0xa0: 0x00020010 0x10008cc2 0x00004810 0x00027482
>      0xb0: 0x10810000 0x00000000 0x00000000 0x00000000
>      0xc0: 0x00000000 0x0000001f 0x00000000 0x00000000
>      0xd0: 0x00000000 0x00000000 0x00000000 0x00000000
>      0xe0: 0x00000000 0x00000000 0x00000000 0x00000000
>      0xf0: 0x00000000 0x00000000 0x00000000 0x00000000
> 
> 


-- 
-----------------------------------------------
                SAITOH Masanobu (msai...@execsw.org
                                 msai...@netbsd.org)

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